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Observer crowleyuk
Observer
466 Views
Registered: ‎04-13-2018

Implimenting XAPP524/1017 CLK Alignment

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Hi there,

I've been attempting to impliment the clock deskew circuit described in XAPP524 and XAPP1017.

Running the post implimentation timing simulation, my circuit correctly adjust taps until a rising edge from stable low to stable high has been detected on the output of the ISERDES.

This isn't the case when I program the actual hardware unfortunatly.

The clock I am capturig is a 360MHz signal from an imaging sensor, it is free running once the sensor has been started.

Using an ila on the design, clocked from the bufr driven by the incoming 360MHz clock / 8 the output of the ISERDES is stuck at 0 (8 bit mode).

I am using a BUFIO as the CLK input, and a bufr with divider at 8 for the CLKDIV of the ISERDES in networking mode.

Now this is where it gets interesting,

If I replace the bufio with a bufr, no divider I start to see junk on the ISERDES output, when my tap is set to 0 in the IDELAY block. after 2 taps, the data returns to a steady 0 all the way until the taps over flow from 31 to 0, where junk will then become present on the ISERDES output.

With a clock period of 2.778ns, I would have expected to see both edges of the clock when cycling through all 31 taps.

I have measured the incoming clock and it is indeed 360MHz.

Any advice on what my next steps should be?

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1 Solution

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Observer crowleyuk
Observer
405 Views
Registered: ‎04-13-2018

Re: Implimenting XAPP524/1017 CLK Alignment

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Turns out I had my reset signal to the idelayctrl module wrong.

Created a quick and dirty 32 flipflop delay from reflk to the reset input and everything sprang into life as expected.

No idea why it passed simulation.

View solution in original post

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2 Replies
Observer derrickg
Observer
455 Views
Registered: ‎05-04-2016

Re: Implimenting XAPP524/1017 CLK Alignment

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What clock are you using to set the delay on your idelay block?  I typically use 200MHz for a ~78ps delay per tap.

I ended up adapting the XAPP.  I have set my idelay blocks for the data lines at a fixed 15 taps, and then vary the taps for the clock's idelay block.  That has given me much better results because I can sync even if the clock is already late.

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Observer crowleyuk
Observer
406 Views
Registered: ‎04-13-2018

Re: Implimenting XAPP524/1017 CLK Alignment

Jump to solution

Turns out I had my reset signal to the idelayctrl module wrong.

Created a quick and dirty 32 flipflop delay from reflk to the reset input and everything sprang into life as expected.

No idea why it passed simulation.

View solution in original post

0 Kudos