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Explorer
Explorer
4,869 Views
Registered: ‎07-29-2009

Interface possibilities

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I am designing a board with a zynq z030. I have differential clock drivers that can be either HSDS, LVDS, LVPECL, or LCPECL (selectable). We did not place those signals into an HP bank that might have DCI. The drivers have a resistor to ground and an AC coupling capacitor before entering the FPGA at an MRCC input (bank 13) and MGTRefClk.  What would be the best choice (or ANY choice) for one-way, differential receiver input technology at the MRCC input? I'm looking at UG471 and I would like help in choosing the optimum standards for both transmitter (TI chip)  and receivers (Xilinx Zynq7000) given my limited option in terms of external components.

 

Can you make any recommendations?

Regards,

Kurt

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Xilinx Employee
Xilinx Employee
8,316 Views
Registered: ‎07-23-2015

Re: Interface possibilities

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Do you have DIFF_TERM enabled? It should be disabled as mentioned in the conditions of UG471 I referred to

 

can you share your UCF constraint for this clk signal & your IBUFDS instantiation in your code?

 

 

- Giri
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Xilinx Employee
Xilinx Employee
4,830 Views
Registered: ‎07-23-2015

Re: Interface possibilities

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Since Bank 13 is an HR Bank, I would suggest choosing LVDS so that you can use DIFF_TERM provided you power Bank 13 with 2.5V. LVDS doesn't need DCI. 

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Explorer
Explorer
4,820 Views
Registered: ‎07-29-2009

Re: Interface possibilities

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The port is not bi-directional, and it's 3.3V. The port is receive-only. I noticed that in Vivado the LVDS is red when selected, but it does let me choose the LVDS2.5. I don't see an option to use "DIFF_TERM" in the I/O Ports tab in Vivado (after synthesis). Is this something that is added by hand in TCL, or is there another way / place to enter it when using Vivado?

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Xilinx Employee
Xilinx Employee
4,814 Views
Registered: ‎07-23-2015

Re: Interface possibilities

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@petersk I meant LVDS_25 since that is  available for HR bank. LVDS is for HP. Regarding DIFF_TERM, you can set it in UCF file 

 

Check page#49 http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Explorer
Explorer
4,807 Views
Registered: ‎07-29-2009

Re: Interface possibilities

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Well, as it turns out, I have LVCMOS3.3 on the same bank and it seems like it errors out even using LVDS25.  Do I have any other "compatible" choices on a HR bank?

 

I can AC couple either HSDS, LVPECL, or LVDS and then use in_term; but how do I know what standard to use to ensure nothing is overdriven in the FPGA?

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Xilinx Employee
Xilinx Employee
4,791 Views
Registered: ‎07-23-2015

Re: Interface possibilities

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Ok, can you answer the below to better understand your use case

 

1. LVCMOS33 is the only other IO standard in the Bank? 

2. LVDS_25 you plan to use a inputs right? If so, you should be able to use LVDS_25 as inputs even if VCCO != 3.3V. Check page 92 of Ug471 on conditions that need to be followed in this use case

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Explorer
Explorer
4,779 Views
Registered: ‎07-29-2009

Re: Interface possibilities

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forxilinx33.PNGThat doesn't seem to work. See attached...

forxilinx33_err.PNG

Any thoughts?

 

 

 

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Xilinx Employee
Xilinx Employee
8,317 Views
Registered: ‎07-23-2015

Re: Interface possibilities

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Do you have DIFF_TERM enabled? It should be disabled as mentioned in the conditions of UG471 I referred to

 

can you share your UCF constraint for this clk signal & your IBUFDS instantiation in your code?

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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Explorer
Explorer
4,672 Views
Registered: ‎07-29-2009

Re: Interface possibilities

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I disabled DIF_TERM and it now doesn't error. Now I'm going to try it and let you know if it works without diff-term.

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Xilinx Employee
Xilinx Employee
4,665 Views
Registered: ‎07-23-2015

Re: Interface possibilities

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Since DIFF_TERM is disabled, hope you have a external 100-ohm resistor near the receiver for the LVDS signal

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Explorer
Explorer
3,064 Views
Registered: ‎07-29-2009

Re: Interface possibilities

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I have a 50 Ohm to ground on each leg.  Do you think that might work?

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Xilinx Employee
Xilinx Employee
3,063 Views
Registered: ‎07-23-2015

Re: Interface possibilities

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LVDS needs a 100-ohm termination across the P& N signals as shown below. LVDS is a current mode driver and the 100 ohm is what produces the differential swing voltage.

With DIFF_TERM disabled, you need the external resistor like in Figure 1-70 below

 

lvds_term.JPG

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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