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Participant herand
Participant
659 Views
Registered: ‎07-24-2017

Interior of a LUT5?

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Hello,

 

I want to make us of a programmable delay line (see FPGA-based TRNG , page 5) in a Zynq-7 device, where they make use of the different propagation delays within  a LUT. A similar interior of the interior of an Altera LUT is given in this link .

 

I am looking for some simular documentation on LUTs, especially LUT 5 which is the most basic building block, in order to see the mapping of the A - D inputs to the output, which I then can utilize for my purpose. However, UG474 and UG 953 give no deeper insight on this building block and all my other attempts of searching for this information failed.

 

Can you help me by either pointing me to the correct documentation, where I can see the interconnectivity within a LUT5?

 

Thanks in advance and kind regards.

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1 Solution

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Moderator
Moderator
909 Views
Registered: ‎04-18-2011

Re: Interior of a LUT5?

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you already posted a similar thread... 

 

We might consider closing this one. Is that ok?

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Moderator
Moderator
910 Views
Registered: ‎04-18-2011

Re: Interior of a LUT5?

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you already posted a similar thread... 

 

We might consider closing this one. Is that ok?

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Don’t forget to reply, kudo, and accept as solution.
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Participant herand
Participant
627 Views
Registered: ‎07-24-2017

Re: Interior of a LUT5?

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Oh... I got a message that this post was deleted because one of the links might have violated the forums guideline and therefore created a new topic without the links. Sorry about that and of course, this post can be closed.

If anybody is interested, here is the new thread, where I got really god explanations:

https://forums.xilinx.com/t5/7-Series-FPGAs/Interior-switching-of-LUT5-SRAM/td-p/835012/

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