Is Binary Counter v12.0 supported for Zynq Z-7020?

[rhc110again]

PG121 says Binary Counter v12.0 is supported for the Zynq-7000.  Vivado 2017.2.1 says:

"The IP xilinx.com:ip:c_counter_binary:12.0 is not supported. Please contact your Xilinx representative with feedback."

I have a Z-7020.  Should PG121 actually say that Zynq Z-7030 and above support Binary Counter v12.0???  As in, only Kintex fabric supports it, not Artix?

[ryana]

Hello @rhc110again,

I did a quick test with a Z-7020 device in Vivado 2017.2, 2017.2.1, and 2017.3 and in all versions there were no issues adding this IP to a regular project or a block design. I suspect there may be something going on related to your install or your licensing.  Are you using the 2017.2.1 WebPack install or the full version?

[rhc110again]

Hello @ryana,

I'm running a full license, not WebPack.  

Note that the Performance and Resource Utilization page for the IP only lists Ultrascale, Kintex, and Virtex parts.  No Artix, and no Zynq-7000s.

The error message I get makes the following suggestion:

The IP xilinx.com:ip:c_counter_binary:12.0 is not supported. Please contact your Xilinx representative with feedback. To get a list of supported IP, run this TCL command in the TCL console: get_ipdefs -filter SUPPORTS_MODREF==1

So I ran that command and got:

get_ipdefs -filter SUPPORTS_MODREF==1
xilinx.com:ip:dds_compiler:6.0 xilinx.com:ip:fifo_generator:13.1 xilinx.com:ip:duc_ddc_compiler:3.0 xilinx.com:ip:vio:3.0 xilinx.com:ip:cmpy:6.0 xilinx.com:ip:xbip_multadd:3.0 xilinx.com:ip:cic_compiler:4.0 xilinx.com:ip:cordic:6.0 xilinx.com:ip:xfft:9.0 xilinx.com:ip:dft:4.0 xilinx.com:ip:mult_gen:12.0 xilinx.com:ip:ila:6.2 xilinx.com:ip:c_addsub:12.0 xilinx.com:ip:xbip_dsp48_macro:3.0 xilinx.com:ip:dist_mem_gen:8.0 xilinx.com:ip:blk_mem_gen:8.3 xilinx.com:ip:fir_compiler:7.2

No Binary Counter v12.0!

Please note that I customized the IP from the Vivado IP Catalog GUI, which one would expect to filter out non-supported IP, especially when one clicks the "Hide disabled and incompatible IPs" button within the Catalog GUI...

Thanks for any further advice.

[ryana]

Hello @rhc110again,

Can you please go through the steps to produce the error message?  Also include the specific FPGA you're targeting.

[rhc110again]

Hello @ryana,

I'm targeting a xc7z020clg484-2i

I'm running in project mode.  I have a block diagram top level that includes the PS, AXI interconnect, AXI BRAM controller, Block Memory Generator, Clocking Wizard, and my RTL.  All of my code is packaged into a single RTL block module that includes the connections to IO pins, the PS, and the peripherals (AXI Interconnect, Block Memory Generator, and Clocking Wizard).

When I want to add IP to my RTL, I do the following:

1. Open the IP Catalog

2. Select the IP (Binary Counter, in this case), and click Customize IP

3. Customize the IP in the GUI

4. Generate with Global synthesis selected

5. Open the template in the synth folder under sources_1/ip/<customIPname>/

6. Use the template to instantiate

That process has worked for several other IPs.  I can complete all of those steps when adding a Binary Counter IP to my project as well, but I get the error reported in the original post when I try to synthesize (or simulate).

[ryana]

Hello @rhc110again,

Let me give this a quick test and I'll get back to you with the results.

[ryana · Accepted solution]

Hello @rhc110again,

The Binary Counter is supported by the Zynq 7000 but the IP itself doesn't support module references in Vivado 2017.2.1

With your flow I was able to reproduce the error in 2017.2.1 but when I did it in 2018.1 there was no error.  Next I ran the get_ipdefs -filter SUPPORTS_MODREF==1 command and saw that Binary Counter was supported.  What was strange was that I couldn't run that command in 2017.3 or 2017.4.  I did a quick test in 2017.3 and it seems to work.

In order for your current flow to work you'll have to upgrade to 2017.3

[rhc110again]

Thanks for digging into it @ryana  It's always nice to have closure!  I ended up using the DSP48 macro IP to implement a P (output) + C (carry-in) equation.  I'd probably recommend the DSP48 macro IP to other users in a similar situation as well; it gives you a little more understanding and control over the resource, with minimal additional investment of time.