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Registered: ‎02-11-2019

Is the serdesstrobe pulse in post route simulation misrepresented?

I've set up simple and complexoserdes2 clocking schemes and have found that the serdesstrobe from the bufpll doesn't agree with the fpga editor.

It seems like the serdesstrobe is more complex than the tools imply, or that perhaps it's actually located on the edge, and there's no routing from the bufpll to it's location on the edge.

I've also seen comments that the documentation of this system is intentionally vague.

So here's the issue: I see 1.5ns routing for ioclk to the edge oserdes, and the serdesstrobe is specified as 1.7ns.

But in post route simulation the serdesstrobe has 0 ns delay. The ioclk is accurate, but the serdesstrobe is not.

What's up with that?

More information:   If you post route simulate this serdesstrobe signal at the bufpll,  and also the ioclk signal,  then you have visual data in the simulator.  Those who've used the simulator know, if you add a signal that wasn't recorded previously, it'll be blank until you run the sim some more.

So, if you follow the strobe and clock to their destination oserdes2, you can pick up those signals across the 1.9ns and 1.7ns routing.

But when you add them, the IOCE already has identical data to the SERDESSTROBE signal.  In other words, they are the same signal.  There is no routing delay as specified in the fpga editor.

The clock signal CLK0 however does not show up with the IOCLK data.  That's because it has the proper routing delay and is not the same signal.

This poses a problem at higher speeds because the IOCLK has a skew, but the strobe does not.  The IOCLK shifts out of alignment and can skip a pulse.  On the sim it looks illegal (rising edge does not have any setup or hold).

One might try to fix this by using phase shifting, but the serdesstrobe signal does not follow the datasheet specified alignment to GCLK.  It also phase shifts so that you are still without  proper setup and hold at higher speeds.

 

 

 

 

 

 

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