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Registered: ‎03-14-2019

Is there internal bias for LVDS_25 input in Artix 7A200T

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Hi there,

I am reviewing a schemtaic, TI's LMK00301 clock buffer is used to clock Artix XC7A200T-2FFG1156C at MRCC pin AG29/AG30 of Bank13 and this bank powered by 2.5V, we will use LVDS_25 fomat for this clock input pair.   f=200MHZ. 

LMK00301---> 0.1uF cap ---> FPGA MRCC pin pair.

The output spec of LMK00301 is Vocm = 1.125~1.375V with typ. 1.25V, Vod(swing)=250~450mV with typ.400mV (https://www.ti.com.cn/document-viewer/LMK00301/datasheet/specifications#snas512292)

 

Here are my questions: 

1. According to UG471(page91-93) and DS181 (table 11), I think LMK00301 can DIRECTLY drive 7A200T (dc coupled without any other RC compnents), AC-coupling is unnecessary. Because Vocm and Vod swing falls within (satisfy) 7A200T's input spec range. So this sch seems incorrect. How do you think?

2. If they insist using AC-coupling, my concern is , is there internal bias voltage for LVDS_25 inputs in 7A200T? I spend a lot of time but can not find the corresponding content in Xilinx docs. 

(1) If there is no internal bias, the simple AC coupling as this SCH does should be incorrect, and additioanal external R_bias network is needed, or else the device might be damged due to LVDS negative votage swings after AC capacitors. 

(2) If there is internal bias, what's its bias voltage and pull-up/down resistance? 

By the waym in this thread, https://forums.xilinx.com/t5/Implementation/Internal-LVDS-termination-with-bias/td-p/973266, @markg@prosensing.com mentioned that "Although an internal 100-ohm termination can be activated for LVDS, there is no FPGA internal bias voltage (as shown in your sketch). " but I do hope to find an official doc that confirms this.

3.  Although internal 100ohm diff termination ON/OFF is up to desinger, it is an optional setting,  I do think it is a MUST to enable it for LVDS_25 input as Reuqired by LVDS standard. We know LVDS is current driver and reuqires 100ohm load across P/N lines to close the current path. IS my understanding correct ?

4. Suppose user do not enable DIFF_TERM 100ohm,  there could be signal integrity issue.  Here also comes my question : what is the differential input impedance ? It should be high-impedance about kilio-ohms, but I do hope to know the resistance number.

Thanks and happy weekend!

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Registered: ‎02-09-2017

Hi @xytech,

That is correct. You can still enable the internal DIFF_TERM so you do not need to add a physical 100 ohm resistor to your PCB.

Replying to your questions 3 and 4.

3.  Although internal 100ohm diff termination ON/OFF is up to designer, it is an optional setting,  I do think it is a MUST to enable it for LVDS_25 input as Required by LVDS standard. We know LVDS is current driver and requires 100ohm load across P/N lines to close the current path. IS my understanding correct ?

Answer: That is correct. When using LVDS standard, it is mandatory to have the  100ohm termination across the P and N terminals. The only reason why this feature is optional in the FPGA is to allow customers to either use it or to implement their external resistor. One of the two must be present.

 

4. Suppose user do not enable DIFF_TERM 100ohm,  there could be signal integrity issue.  Here also comes my question : what is the differential input impedance ? It should be high-impedance about kilo-ohms, but I do hope to know the resistance number.

Answer: From the top of my mind, I don't remember the impedance between pins when the device is configured. But I must say that this should not even be a concern because the differential input must be present. If the user do not either enable the internal DIFF_TERM or  add and external resistors, their design is incorrect and not compliant to the TIA/EIA-644. It may also damage the device.

Thank you,

Andre Guerrero

Product Applications Engineer

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Registered: ‎01-22-2015

@xytech 

I think LMK00301 can DIRECTLY drive 7A200T (dc coupled without any other RC compnents), …… Because Vocm and Vod swing falls within (satisfy) 7A200T's input spec range.  So this sch seems incorrect. How do you think?
I agree with you that LVDS output of the LMK00301 is compatible with LVDS input of the Artix-7.  I also agree that the AC-coupling circuit you describe needed further study.

"Although an internal 100-ohm termination can be activated for LVDS, there is no FPGA internal bias voltage (as shown in your sketch). " but I do hope to find an official doc that confirms this.
For UltraScale devices, UG571 often mentions the internal DSQ_BIAS for LVDS inputs.  There is no mention of an internal bias for LVDS in the similar document, UG471, for 7-Series devices (eg. Artix-7).  So, I cannot provide the official doc that you want.  I also cannot provide the official doc saying the Artix-7 does not have an internal coffee machine : - )

However, we know that Fig 1-72 in UG471(v1.10) is a correct way to AC-couple, DC-bias, and 100-ohm-terminate a LVDS clock input to a 7-Series FPGA.  So, if you use this circuit (and follow guidance on pages 91-93 of UG471) then things will work properly.

So, the question is, should you AC-couple the clock input to the Artix-7 - or not? 

An advantage of AC-coupling the LVDS clock is that it protects the FPGA from damage during power-up.  For example, Table 2 of the Artix-7 datasheet, DS181, shows a specification of 10mA for IIN (maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode).  These clamp diodes connect from the FPGA pin to VCCO and GND.  The clamp diode forward bias voltage is about 0.5V (ref  AR#37347).

If you do not AC-couple LVDS from LMK00301 and the LMK00301 powers up before VCCO on the FPGA, then the LMK00301 must limit current on each LVDS trace to less than 10mA (ie. less than IIN specification for FPGA).  However, page 10 of LMK00301 datasheets shows that LVDS outputs have short-circuit current (ISA, ISB) of 24mA!   This 24mA current could damage the IO pins of the FPGA.

So, I recommend that you AC-couple the LMK00301 clock buffer to the FPGA using the circuit shown by Fig 1-72 in UG471.

PS:  AC-coupling is suitable for LVDS clock inputs and is generally not suitable for LVDS data inputs – unless the data inputs have special coding (eg. Manchester).

Cheers,
Mark

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Registered: ‎03-14-2019
Hi mark, @markg@prosensing.com Thanks for detials reply. We can control the power up sequence of LMK00301 and FPGA, so that is not a problem when using DC coupled configuration. By the way , do you have any comments on my 3rd and 4th questions? thanks.
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Hi @gnarahar and @anunesgu

I found this two thread where both of you mentioned the answer to my question2 is NO: There is no internal bias inside 7A200T, When AC coupled to LVDS25 inputs, even if the Bank supply votlage is correct (2.5V for HR IO), we should still add external R_bias network as figure1-72 of UG471 shows. But we can enable the 100ohm internal termination (DIFF_TERM = TRUE) to save the external 100ohm in fig1-72. Did my perception correct?

 

Quote:

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Do-internal-LVDS-terminators-work-with-AC-LVDS/td-p/845379, [key information on last section of this thread]

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Pin-Assignment/m-p/814830#M24477, [key information on last section of this thread]

 

By the way,

would you help take a look at my questions , especially Q3 and Q4 ? I hope to get the input impedance value when DIFF_TERM is False. Thank you very much!

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Registered: ‎02-09-2017

Hi @xytech,

That is correct. You can still enable the internal DIFF_TERM so you do not need to add a physical 100 ohm resistor to your PCB.

Replying to your questions 3 and 4.

3.  Although internal 100ohm diff termination ON/OFF is up to designer, it is an optional setting,  I do think it is a MUST to enable it for LVDS_25 input as Required by LVDS standard. We know LVDS is current driver and requires 100ohm load across P/N lines to close the current path. IS my understanding correct ?

Answer: That is correct. When using LVDS standard, it is mandatory to have the  100ohm termination across the P and N terminals. The only reason why this feature is optional in the FPGA is to allow customers to either use it or to implement their external resistor. One of the two must be present.

 

4. Suppose user do not enable DIFF_TERM 100ohm,  there could be signal integrity issue.  Here also comes my question : what is the differential input impedance ? It should be high-impedance about kilo-ohms, but I do hope to know the resistance number.

Answer: From the top of my mind, I don't remember the impedance between pins when the device is configured. But I must say that this should not even be a concern because the differential input must be present. If the user do not either enable the internal DIFF_TERM or  add and external resistors, their design is incorrect and not compliant to the TIA/EIA-644. It may also damage the device.

Thank you,

Andre Guerrero

Product Applications Engineer

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