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Adventurer
Adventurer
454 Views
Registered: ‎10-12-2018

Kintex 7 Dual Edge Flip-Flops

Hello to all,

I have looked through Kintex-7 device and could not find any information that explicitly indicates that it supports dual edge flip-flops. I am supposed to design an IP with double data rate transfer, and I wanted to know if there is such a flip-flop; Or should I take two different sets of flip-flop each for both edges of the clock?  

I would be really grateful if anybody could also suggest me some references and tips.

Thank you very much in advance.

Regards,

Amir

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4 Replies
Scholar drjohnsmith
Scholar
447 Views
Registered: ‎07-09-2009

Re: Kintex 7 Dual Edge Flip-Flops

IOB registers on th epins are DDR,

    so support both edge of the clock.

 

DDR is not possible inside the FPGA, as internal FDRE are single edge ,

    but IOB its very normal to use ODDR and IDDR.

 

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf?bcsi_scan_76a858e05751204b=0&bcsi_scan_filename=ug471_7Series_SelectIO.pdf

page 127,

 

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Adventurer
Adventurer
434 Views
Registered: ‎10-12-2018

Re: Kintex 7 Dual Edge Flip-Flops

Hi @drjohnsmith 

Thank you very much for your quick reply.

I need DDR inside the FPGA, that means I should go through two parallel sets of flip-flops sensitive to both edges of the clock.

Do you know any kind of references that can be helpful for this purpose?

Thank you in advance.

Regards,

Amir

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Scholar watari
Scholar
430 Views
Registered: ‎06-16-2013

Re: Kintex 7 Dual Edge Flip-Flops

Hi @amir.massah 

 

Would you refer page 109 on following document ?

 

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

Best regards, 

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Scholar drjohnsmith
Scholar
414 Views
Registered: ‎07-09-2009

Re: Kintex 7 Dual Edge Flip-Flops

I might have confused ,  sorry.

both the IDDR / ODDR and the FDRE are on th efpga chip, its just teh  IDDR and ODDR are on the outside , user facing, whilst FDRE's are not user facing..

inside the FPGA, htings are always single clock edge, not both edge,

    the IDDR and ODDR allow one to receive / transmit DDR signals

    and then inside th efpga, you have two paths , not one,  both on the same clock edge.

 

 

 

  

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