04-15-2019 06:39 AM
Hello to all,
I have looked through Kintex-7 device and could not find any information that explicitly indicates that it supports dual edge flip-flops. I am supposed to design an IP with double data rate transfer, and I wanted to know if there is such a flip-flop; Or should I take two different sets of flip-flop each for both edges of the clock?
I would be really grateful if anybody could also suggest me some references and tips.
Thank you very much in advance.
04-15-2019 06:51 AM - edited 04-15-2019 06:52 AM
IOB registers on th epins are DDR,
so support both edge of the clock.
DDR is not possible inside the FPGA, as internal FDRE are single edge ,
but IOB its very normal to use ODDR and IDDR.
04-15-2019 08:28 AM
Thank you very much for your quick reply.
I need DDR inside the FPGA, that means I should go through two parallel sets of flip-flops sensitive to both edges of the clock.
Do you know any kind of references that can be helpful for this purpose?
Thank you in advance.
04-15-2019 08:38 AM
04-15-2019 09:15 AM
I might have confused , sorry.
both the IDDR / ODDR and the FDRE are on th efpga chip, its just teh IDDR and ODDR are on the outside , user facing, whilst FDRE's are not user facing..
inside the FPGA, htings are always single clock edge, not both edge,
the IDDR and ODDR allow one to receive / transmit DDR signals
and then inside th efpga, you have two paths , not one, both on the same clock edge.