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Participant xilinx.fpga.user
Participant
556 Views
Registered: ‎11-22-2017

Kintex-7: MMCM Dynamic Phase Shift works Intermittently

Hello:

      In our Kintex-7 (XC7K325tffg900-2) design we have eight MMCMs that use dynamic phase shift. Dynamic phase shifting works reliably on four out of these eight MMCMs. On the remaining four MMCMs dynamic phase shift works intermittently about 50% of times. Attached PDF file shows a block diagram of interface signals of these two types of MMCMs. The MMCMs have 200 MHz clock input and 100 MHz PSCLK signal frequency. Four of these MMCMs have 200 MHz clock output where the dynamic phase shift works reliably. But the remaining four MMCMs where the clock output is 100 MHz dynamic phase shift works intermittently. The only difference between the two types of MMCMs is the output clock frequency. The way we interface with them is the same.

      I am attaching screenshots from ILA showing how we drive 'psen' signal and how 'psdone' is generated by MMCM. Each of the eight MMCMs we use are associated with a different clock in our design. I am using one from the working set and one from the non working set of MMCMs as an example. The clock 'sge2' is for the working set, this image shows signals like 'psen_sge2' and 'psdone_sge2'. The clock for the non-working set 'c2e1' shows signals like 'psen_c2e1' and 'psdone_c2e1'. I am attaching 3 screenshots from ILA. One for 'sge2' shows working case. Two more screenshots are for c2e1, one shows the case of intermittenly working and the other shows intermittenly not working dynamic phase shift. For the clock c2e1 the interface signals behave the same way in working and non-working case, this is what I am tryting to show with the screenshots. The only difference between the working and non-working set is the clock output frequency. When the clock otuput is 200 MHz (same as input clock frequency) dynamic phase shift work. When the clock output is 100 MHz dynamic phase shift works intermittenly. The screenshot file names are

sge2_200mhz_op_shift.jpg  (shows working case, 200 MHz clock output, works reliably)

c2e1_100mhz_op_shift.jpg (shows working case, 100 MHz clock output, intermittenly works)

c2e1_100mhz_op_noshift.jpg (shows non-working case, 100 MHz clock output, intermittently fails)

   

       Please help us get this issue resolved.

Thank you so much.

Best regards,

      

0 Kudos
10 Replies
542 Views
Registered: ‎09-17-2018

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

I suggest,

That your design is missing design contstraints, or has clock crossing domains not using synchronizers (resulting in metastability or data errors).

(The most common causes of intermittant behavior is the result of unconstrained paths).

Using the phase shifted MMCM output clock as the clock for phase shifting is not recommended as timing closure is not guaranteed (as the tool may not know the phase i the case of dynamic phase control).

l.e.o.

 

Participant xilinx.fpga.user
Participant
518 Views
Registered: ‎11-22-2017

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

Hello lowearthorbit:

      Thank you so much for your feedback. I was under the impression that for clocks generated from output of MMCM or PLL Vivado will automatically constrain them as clocks of correct frequency. But I will try out your suggestion.

      Thank you so much.

Best regards,

0 Kudos
509 Views
Registered: ‎09-17-2018

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

If you have a constraint for the input clock, all output clocks should get properly constrained automatically,

l.e.o.

 

 

Historian
Historian
504 Views
Registered: ‎01-23-2009

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

If you have a constraint for the input clock, all output clocks should get properly constrained automatically,

To expand on this (and the previous response)...

"If you have a constraint for the input clock, all output clocks should get properly constrained automatically for the initial (static) condition"

The dynamic phase shift is (as the name implies) dynamic. Static timing analysis cannot analyze something that is dynamic.

So if you start with all N of your clocks with a 0 dynamic phase shift, the tool will determine the requirements of the paths between the clock domains based on this 0 phase shift (therefore 5ns setup requirement and 0ns hold requirement on every path). The moment you start shifting one of the clocks forward, then the paths between that clock and any other clock are no longer properly constrained - if you shift it forward 100ps, then the setup requirement for these paths would no longer be 5ns, but 4.9 and the hold requirement would be 100ps. But this is not what static timing analysis designed for and hence your design (as timed and implemented) could exhibit unreliable behavior due to incorrect constraints.

The moment you start using dynamic phase shifts, you leave the realms of static timing analysis - you have to put some kind of clock exception (and possibly a clock domain crossing circuit) between the dynamic domain and any other domain. If the magnitude of the phase shift is bounded (you will never shift more than X forward or backward), you can put exceptions on the intra-clock paths so that static timinig analysis can design for the worst combination - but this must be done manually by the user - there is no way for the tools to understand the maximum value of a dynamic shift.

In the worst case, if the dynamic shift is unbounded, then the dynamic clocks need to be treated as mesochronous with respect to the static (or other dynamic) clocks - in which case you need a proper clock domain crossing circuit (CDCC) with proper constraints to move data between the domains.

All this being said, I don't really understand your original post - when you say the "intermittently working dynamic phase shift" what do you mean? Do you mean the clock doesn't actually shift, or that the system no longer works, (or something else). Exactly what is the behaviour of a the system when it "isn't working"?

Avrum

Scholar drjohnsmith
Scholar
497 Views
Registered: ‎07-09-2009

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

Your going to have to forgive us, I never was much good at spot the ball.

   but I can't see any differenc in the three plots you have shown !

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Participant xilinx.fpga.user
Participant
468 Views
Registered: ‎11-22-2017

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

Hello lowearthorbit:

      Thank you so much for your feedback. Yes I had also assumed that with input clock being constrained the output clocks going through MMCM will be constrained. I am double checking the timing reports.

      Thank you so much.

Best regards,

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Participant xilinx.fpga.user
Participant
465 Views
Registered: ‎11-22-2017

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

Hello avrumw:

      Thank you so much for your feedback. After going through MMCM the clock signal and the logic clocked by it does not interact with rest of the logic running from different clocks. Output of MMCM drives some flops and a combination of this logic shows up on output pins. For our system to work correctly we look at the signal on output pin. When "Intermittently" things work we see that the output signal is shifted by appropriate amount. Sometimes the output signal does not get shifted at all which I had considered a non-working condition. But I will double check everything based on your feedback.

       Thank you so much.

Best regards,

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Participant xilinx.fpga.user
Participant
458 Views
Registered: ‎11-22-2017

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

Hello drjohnsmith:

      Thank you so much for your feedback. Yes the three plots don't show any difference. I am trying to drive the MMCMs in the same way. But when the MMCM output clock is 200 MHz the logic it drives works correctly everytime. But in the case of MMCMs whose output clock is 100 MHz the logic it drives generates a signal for an output pin which does not show expected dynamic phase shift, which I considered an non-working case.

      Thank you so much.

Best regards, 

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Scholar drjohnsmith
Scholar
455 Views
Registered: ‎07-09-2009

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

can you show us a plot that does show the difference please .

   

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Participant xilinx.fpga.user
Participant
434 Views
Registered: ‎11-22-2017

Re: Kintex-7: MMCM Dynamic Phase Shift works Intermittently

Hello drjohnsmith:

      Thank you so much for your feedback. Output of MMCMs drives some logic, output from this logic shows up on IO pins. I will try to bring output of MMCMs directly on IO pins so that we can see the differences. As you have suggested I will collect this data to look at the differences.

      Thank you so much.

Best regards,

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