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kenyang
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Registered: ‎06-13-2018

Kintex-7 some bank VCCO=3.3 V. Output IOstandard type=SSTL18_II or HSTL_II_18. Have any damage for this FPGA?

An FPGA bank voltage=3.3 V. All IO pads of this bank are output type, the IOSTANDARD of these pins are LVCMOS33 initially.

However, the pulse duty of these output pins are bad as the data rate over 200Mbps.

I changed the IOSTANDARD from LVCMOS33 to be SSTL18_II_F or HSTL_II_18_F and got better pulse duty.

The amplitude can up-to 3.1 V. I'm satisfied for this result.

I want to know "May I use SSTL18_II or HSTL_18 as output but VCCO=3.3 V? Have any damage for this FPGA?"

 

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tenzinc
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Registered: ‎09-18-2014

Kenyang,

 

Well, couple things here. Did you try adjusting the drive strength when using LVCMOS33? Is the line terminated properly for a LVCMOS type line? Running a low voltage standard on a higher voltage IO Bank shouldn't necessarily damage the FPGA but do make sure you understand the implications of doing so. There is a reason why we do not support these use cases. I would suggest to run HSPICE simulations if possible to verify the impact on the output to get a accurate analysis on the output characteristics of the scaled VCCO. 

 

Regards,

Tezz

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kenyang
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Registered: ‎06-13-2018

Dear Tezz,

 

Thanks for your answer.

Yes, I have tried many ways for getting better pulse duty, like drive strength/slew rate/short PCB track length/with or without receiver/different IOSTANDARD ...

I used active probe less 1pF capacitance load to monitor the pulse duty. The Drive Strength will effect the ring but no improved in duty. The pulse duty will be over 50% when the data rate is over 200Mbps. It will be obvious after 300Mbps. In fact I need output data rate up to 400Mbps. After many testing I got the conclution: only SSTL18_II_F and HSTL_II_18_F are best solutions.

I supposed the Tioop is the key fact of better pulse duty in fast data rate.

If possible, I want to know the detail risk if I have to set SSTL18_II/HSTL_II_18 output IOSTANDARD as VCCO=3.3 V.

 

BR,

Ken

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tenzinc
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Registered: ‎09-18-2014

If possible, I want to know the detail risk if I have to set SSTL18_II/HSTL_II_18 output IOSTANDARD as VCCO=3.3 V.

-That is not a standard usage or a recommended use case so we don't characterize it. It's up to you to analyze it and determine if it is something you are comfortable doing and taking the risk on if any. Like I said we provide HSPICE models where you can adjust the VCCO for the IO buffer models to see what effect it will have on the IO. If you would not like to go that route you should mod your board to use a 1.8V VCCO for that IO bank. In fact even before this you should have simulated your LVCMOS33 topology to foresee you would run into something like this. LVCMOS are usually meant for lower signal rates. I would also check your VCCO and decoupling to verify that they are up to par. 

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kenyang
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Registered: ‎06-13-2018

Thanks for your suggestion. I downloaded the HSPICE ZIP file but no SSTL18_II model in it.

May I use the sstl15_f_hr.sp to replace sstl18_II or use the IBIS model?

 

BR,

Ken

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klumsde
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Registered: ‎04-18-2011

Hi @kenyang @tenzinc

 

This is not really making sense to me. 

If you take an SSTL18 output, it is just a push-pull output driver like the LVCMOS33 one. 

If you power it with 3.3V after the fact it is going to behave like an LVCMOS33 driver (but you won't really have an idea what the drive and slew rate are)

 

200MHz is pushing it a little bit for LVCMOS33. I would encourage a IBIS simulation with your transmission line included. 

There was a suggestion to try different drive settings on the LVCMOS33 and you said this didn't help. 

You also said that all the IOs in the bank were outputs. 

I have a strong suspicion you are experiencing SSO noise here maybe. 

Can you show us some scope shots of what you are seeing?

Can you try reduce the number of outputs you have in the bank or put some of them on a different phase of the clock?

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kenyang
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Registered: ‎06-13-2018

I found the SSTL18 DC offset has a little bit shift lower voltage than LVCMOS33.

Seems not the SSTL18 output driver just like LVCMOS33.

I have tried one channel output to avoid SSO noise. This is very help for jitter suppression, especially in 400Mbps.

I want to simulate the HSPICE/IBIS model first.

By the way, may I use the LTSPICE, from Linear Tech., to import Xilinx IO model?

BR,

Ken

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