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Visitor
Visitor
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Registered: ‎01-15-2020

Kintex Ultrascale OSERDES clock configuration

My clock question follows very closely to this existing forum post:

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Kintex7-OSERDES-High-Speed-Clocking-with-MMCM/td-p/564351

Since the wording of the documentation is not very clear in terms of what can be a valid correct clock configuration with the BUFIO/BUFR setup, can someone confirm which option below is the recommeded connection to the OSERDES?

OSERDES_option1.png

 

OSERDES_option2.png

 

Note for option 1, the BUFR would use the divide attribute to have the clock at the correct frequency for the data. Option 2 was tried but unfortunately produced bit errors at the output.

Thanks

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Moderator
Moderator
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Registered: ‎08-08-2017

Re: Kintex Ultrascale OSERDES clock configuration

Hi @mphanav 

As i can see you have filed SR for this issue and i have replied to on SR communication.

To summarise.

Option 1 is the valid clocking topology to minimise the skew between CLK and CLKDIV.  (BUFR and BUFIO  can be driven by  MMCMs clock outputs 0-3)

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