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alexkarnaukhov
Explorer
Explorer
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Registered: ‎09-25-2014

LVCMOS33 with VCCO = 1.8V

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Hi all,

 

I`m trying to output 250MHz clock signal on bank with VCCO = 1.8V on pcb. When I`am trying to set IOSTANDARD to LVCMOS18 I get very poor signal quality, even without any load. And poor means really poor, it reach high level only with 10MHz (of course, it can`t be influence of oscilloscope). Setting SLEW to FAST and DRIVE to 24 makes signal just a little better.

In the same time, if I set IOSTANDARD to LVCMOS33 on the same pad, which bank have VCCO = 1.8V, signal becomes normal, even on 250MHz frequency. Device is xc7a35tcpg236-1.

Why I have so bad signal, while using LVCMOS18 and so good with LVCMOS33 on bank with VCCO = 1.8V? Is it normal?

 

Thanks.

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gnarahar
Moderator
Moderator
9,128 Views
Registered: ‎07-23-2015

@alexkarnaukhov When you set the IO Standard to LVCMOS33, do you see the voltage swing between 0 - 3.3V? [I doubt it] 

 

Can you attach your scope shots? Which Pin/Bank is this pin on?

 

Which version of Vivado you using? If using 2016.1, please try in 2016.2 as there is a known issue in 2016.1 of LVCMOS18 output properties not being propagated in partially bonded HR banks. 

 

If you only have 2016.1, the workaround is to set the below parameter before running write_bitstream:

set_param bitgen.EvalUnusedTiles true

 

 

 

 

 

- Giri
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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
The only (potential) difference is the drive strength, which may be different in an LVCMOS33 configured pin vs. an LVCMOS18 configured pin.

You need to check both level 0 and level 1

check this related discussion
https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Output-IOSTANDARD-LVCMOS18-but-Vcco-3-3/td-p/280846
Thanks and Regards
Balkrishan
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gnarahar
Moderator
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9,129 Views
Registered: ‎07-23-2015

@alexkarnaukhov When you set the IO Standard to LVCMOS33, do you see the voltage swing between 0 - 3.3V? [I doubt it] 

 

Can you attach your scope shots? Which Pin/Bank is this pin on?

 

Which version of Vivado you using? If using 2016.1, please try in 2016.2 as there is a known issue in 2016.1 of LVCMOS18 output properties not being propagated in partially bonded HR banks. 

 

If you only have 2016.1, the workaround is to set the below parameter before running write_bitstream:

set_param bitgen.EvalUnusedTiles true

 

 

 

 

 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

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alexkarnaukhov
Explorer
Explorer
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Registered: ‎09-25-2014
Yes, maximum drive strength with LVCMOS33 even smaller (16mA), than with LVCMOS18 (24mA). So this is not an explanation, it is another question.
I`ve read this... It is about Spartan-6. The problem is that I`m porting project from Spartan-6, where was no problems with signal quality with LVCMOS18 and VCCO=1.8V.
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alexkarnaukhov
Explorer
Explorer
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Registered: ‎09-25-2014

Yes! I`m using 2016.1. I'm going to try this now!

UPD: Yeap, set_param bitgen.EvalUnusedTiles true before writing bitstream works as magic.

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