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Observer
Observer
3,054 Views
Registered: ‎12-06-2016

LVDS DIFF TERM Serie7 FPGA

Hi,

If I use the attribute DIFF_TERM = TRUE into LVDS standard input in a HR bank not powered at 2.5V or in HP bank not powered at 1.8V what exactly happens?

The LVDS input in those conditions is supported if DIFF_TRUE = FALSE but if I put  DIFF_TERM = TRUE the differential termination is not guarantee precisely at 100 ohm (as the correct case) or can I cause a damage for the FPGA?

And if I not cause a damage for the FPGA how much is the differential resistor value for the HR and HP banks if not powered precisely at 2.5V and 1.8V respectively?

 

Thanks

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Xilinx Employee
Xilinx Employee
3,036 Views
Registered: ‎08-25-2010

Re: LVDS DIFF TERM Serie7 FPGA

Hi, 

 

Please see https://www.xilinx.com/support/answers/20004.html

 

 

Thanks

Simon

Thanks
Simon
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Observer
Observer
3,028 Views
Registered: ‎12-06-2016

Re: LVDS DIFF TERM Serie7 FPGA

Hi,

thaks for the answer; so from this sentence.

"VCCO supply other than 2.5V results in a non-ideal termination, and is not recommended or supported."

I have understand that the termination is not exactly 100 ohm for this reason is not ideal and not recommended but it is something similar and, if I do this, I have a not ideal termination (bigger or smaller 100 ohm) and I do not cause any damage at the FPGA.

Is it correct?

 

 

Nicola

 

 

 

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Xilinx Employee
Xilinx Employee
2,994 Views
Registered: ‎08-25-2010

Re: LVDS DIFF TERM Serie7 FPGA

Hi Nicola,

It is correct.

 

Thanks

Simon

Thanks
Simon
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