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Visitor
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Registered: ‎04-18-2018

MIPI Rx IP through XADC connector of Digilent Nexys 4 DDR (Artix-7)

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Dear community,

 

We are using the Digilent Nexys 4 DDR board (containing an Artix-7 XC7A100T-CSG324 FPGA) to connect a camera module through a MIPI interface. For this, we are using the “MIPI CSI-2 Rx Subsystem” from the Xilinx IP catalog.

The MIPI interface for our camera module has 2 data lanes and a clock lane, each using a pair of LVDS pins (CAM1_DN0 & CAM1_DP0, CAM1_DN1 & CAM1_DP1 for the data lanes and CAM1_CN & CAM1_CP for the clock lane).

 

On the Digilent Nexys 4 DDR board, we connect this to the JXADC connector, which is in turn connected to the auxiliary analog input pins of the Artix-7. At lines 144 and following in the Nexys4DDR_Master.xdc file in attachment, you can see how exactly these pins are connected.

 

The problem is that I receive the following critical warnings concerning the clock lane pins, which I don’t entirely understand:

 

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/ibufds_clk_inst at B16 (IOB_X0Y136) since it belongs to a shape containing instance MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/bufio_inst. The shape requires relative placement between MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/ibufds_clk_inst and MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/bufio_inst that can not be honoured because it would result in an invalid location for MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/bufio_inst. ["D:/Workdir/Xilinx/Vivado/I-ModelDrivenEngineering/Mipi/Nexys4DDR_Master.xdc":148]

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/ibufds_clk_inst at B16 (IOB_X0Y136) since it belongs to a shape containing instance MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/bufio_inst. The shape requires relative placement between MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/ibufds_clk_inst and MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/bufio_inst that can not be honoured because it would result in an invalid location for MIPI_CSI2_RX/U0/phy/inst/bd_639e_0_phy_0_rx_support_i/slave_rx.bd_639e_0_phy_0_rx_ioi_i/bufio_inst. ["D:/Workdir/Xilinx/Vivado/I-ModelDrivenEngineering/Mipi/Nexys4DDR_Master.xdc":149]

 

Shouldn’t we be able to connect the LVDS clock lane to these pins? If so, where? For the data lane, there seems to be no problem. It appears to be a warning related to the fact that these pins are used as a clock (by the “MIPI CSI-2 Rx” IP block). Maybe there is a setting in this IP block that could override this warning or is it really not possible to connect a MIPI interface to this board?

 

By the way, ignoring this warning results in an “unconstrained logical port” error during bitstream generation, since the pins will be unassigned. So I assume the problem originates from the critical warnings.

 

We already constructed a small PCB according to the XAPP 894 application note from Xilinx, which seems to suggest it should be possible.

 

Maybe I am missing something, but I hope somebody could clear this up for us.

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Community Manager
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Registered: ‎08-08-2007

On error message it is a bit obscure but this can happen with the buffer is a part of the IP and there is probably a PBLOCK that the IBUFDS is apart of it. As you are trying to put a clock on the non _CC pins the placer cannot place it then the PBLOCK "shape" cannot be matched. 

 

1) if I try to connect my MIPI camera to these pins, will this work or did the clock pin pair have to be optimally routed on the Digilent board?

I'm not sure I fully understand your question so apologies if I'm misunderstanding. 

The clock pin pair you are talking about here are the mipi_phy_if_clk pins? 

This clock cannot be on the non Clock Capable pins. 

 

2) if it doesn't, is there a way the MIPI CSI-2 Rx subsystem IP can be told not to require a matched clock pin pair, but a regular matched pin pair instead? The internal clock routing won't be optimal, I know, but could this work?

I dont think so, I think it is a fundamental requirement that the clock is input on the _CC pins so the IP knows how to center the clock/data.

 

 

 

 

 

Thanks,
Sandy

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Contributor
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Registered: ‎04-18-2018

Hi Koen,

 

Here you can find the pinout of your FPGA. https://www.xilinx.com/support/packagefiles/a7packages/xc7a100tcsg324pkg.txt

The second column, pin name, give some information about the pin.

(The name is also written in the xdc provided by Digilent.)

 

Generally, when there is "CC" in the name, you can use it as a clock.

Try to find two available ones.

 

Bests,

Arthur

-------------------------------------------------------------------------------------
Arthur DUMAS, FPGA Engineer, Consultant at ELSYS Design
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@koen.lostrie

 

This topic is still open and is waiting for you.

 

If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions This way, the topic can be completed then. 

 

If this is not solved/answered, please reply to the thread.

 

--Syed

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Hi Arthur,

 

thanks for your quick response, I was not at work and didn't expect it to be that quick ;-)

 

I do know about the clock pins on the Artix-7, but the problem is that on the Digilent Nexys 4 DDR board, the only connector which is routed for matched pin pairs (JXADC), does not connect to an Artix-7 clock pin. I could use another pair of pins on one of the other PMOD connectors, but "Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching" according to the manual on page 21.

 

The JXADC connector connects to the following pin pairs on the Artix-7:

- A13 and A14: IO_L9P_T1_DQS_AD3P_15 and the N version (I used these for data lane 1)

- A15 and A16: IO_L8P_T1_AD10P_15 and the N version (I used these for data lane 2)

- B16 and B17: IO_L7P_T1_AD2P_15 and the N version (I incorrectly used these for the clock lane)

- B18 and A18: IO_L10P_T1_AD11P_15 and the N version (I didn't use these)

 

This means I can only use these pins for the two data lanes of my MIPI CSI-2 interface.

 

The JB connector however contains some multiregion clock input pins:

- G16: IO_L13N_T2_MRCC_15

- H16: IO_L13P_T2_MRCC_15 (=the ONLY pin on the board, which connects to a P-version of a clock input!)

 

As stated above, these pins are not optimally routed for matched pairs, so I'm wondering if this is a feasible option for my 200MHz interface (as the MIPI CSI-2 Rx subsystem manual states at page 13 that it always uses a D-PHY clock of 200MHz).

 

In other words:

1) if I try to connect my MIPI camera to these pins, will this work or did the clock pin pair have to be optimally routed on the Digilent board?

2) if it doesn't, is there a way the MIPI CSI-2 Rx subsystem IP can be told not to require a matched clock pin pair, but a regular matched pin pair instead? The internal clock routing won't be optimal, I know, but could this work?

 

As for the error message I didn't understand why it doesn't just say "this is not a clock input pin", but instead tells me about the bufio_inst pin having to be placed between ibufds_clk_inst and bufio_instAnd what is this "shape" it is referring to?

 

Many thanks for your expertise.

 

Koen

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Community Manager
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Registered: ‎08-08-2007

On error message it is a bit obscure but this can happen with the buffer is a part of the IP and there is probably a PBLOCK that the IBUFDS is apart of it. As you are trying to put a clock on the non _CC pins the placer cannot place it then the PBLOCK "shape" cannot be matched. 

 

1) if I try to connect my MIPI camera to these pins, will this work or did the clock pin pair have to be optimally routed on the Digilent board?

I'm not sure I fully understand your question so apologies if I'm misunderstanding. 

The clock pin pair you are talking about here are the mipi_phy_if_clk pins? 

This clock cannot be on the non Clock Capable pins. 

 

2) if it doesn't, is there a way the MIPI CSI-2 Rx subsystem IP can be told not to require a matched clock pin pair, but a regular matched pin pair instead? The internal clock routing won't be optimal, I know, but could this work?

I dont think so, I think it is a fundamental requirement that the clock is input on the _CC pins so the IP knows how to center the clock/data.

 

 

 

 

 

Thanks,
Sandy

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Visitor
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Registered: ‎04-18-2018

@sandrao,

 

Thank you for your answer. The clock pin pair I'm talking about is a third differential lane (besides the two data lanes) on the MIPI interface. I don't know their internal name of the IP block, but on the generated VHDL they are called clk_lp_rxp and clk_lp_rxn.

 

I also asked the Digilent forums if someone ever connected a MIPI interface to this Nexys-4 board and apparently, it seems impossible.

 

Thanks again for your expertise.

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