07-14-2015 11:23 AM
I am having descepencies between the dynamic phase shift increments of the MMCM module on a MicroZed board with XC7Z020. I would like to shift the phase of CLKOUT1 with respect to CLKOUT0. Simulation gives me the phase shift that I would expect based on the 7 Series FPGAs Clocking Resources User Guide and the parameters that I have set. However, these increments are exactly doubled when implemented on the board and measured with an oscilloscope.
I am feeding a 100MHz clock into the MMCM, multiplying it by 10, then dividing by 10 to get the same 100MHz frequency on channels 0 and 1.
CLKFBOUT_MULT_F (M) = 10
CLKIN1_PERIOD (Fclkin) = 10
CLKOUT0_DIVIDE_F (O_0) = 10
CLKOUT1_DIVIDE (O_1) = 10
DIVCLK_DIVIDE (D) = 1
According to the 7 Series FPGAs Clocking Resources User Guide:
Fvco = Fclkin * (M / D)
Fout = Fclkin * (M / D*O)
Phase shift increment = 1 / (56 * Fvco)
With these parameters, I expect that Fvco is 1GHz and that the fine phase shift should be in increments of ~18ps. In simulation, shifting the phase by 280 increments results in the two signals being 180 degrees out of phase. When implemented on the MicroZed, a phase shift of 140 increments gives me the same result. 280 increments will bring the two signals back into phase with each other.
To me, it seems that the most likely reason for this happening is that the MMCM is receiving a clock that is half as fast in implementation than in simulation. I have checked many times that the 10ns period in my testbench matches the 100MHz clock in implementation. I am measuring MMCM output clocks of 100MHz on the Microzed which match the 100MHz output clocks in simulation.
What can be causing this difference?
Attached are the instantiation of the MMCM with dynamic phase shift logic and the associated test bench.
07-14-2015 11:59 AM
07-14-2015 12:37 PM
Yes: assert PSEN for a single PSCLK cycle.
As for everyone's help...that has to be the easiest "everyone" ever had it: you answered your own question.