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Observer anushakodimela
Observer
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Registered: ‎02-14-2019

Maximum Frequency limits for FPGA from the oscillator

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The Digilent nexys2 board has built in oscillator which generates 50 Mhz clock and the Basys2 board has silicon oscillator with user settable frequency of (25/50/100Mhz). I want to use much higher clock for the Basys2 Spartan 3E board using the second oscillator socket  say above 500 Mhz.Can I do that?

What are the minimum and maximum frequency ranges that Xlinx Spartan 3E-500 FPGA and  Xlinx Spartan 3E-100 FPGA would accept from an oscillator?

Are we supposed to check the DC and AC Switching characteristics of the FPGA device data sheet table 32 Frequency Max_BUFG value (as attached in screenshot for Spartan7 )?Why does Spartan 3E  DC and AC Switching characteristics data sheet doesn't have this table?

Kindly suggest

Thanks and Regards

Anusha Kodimela

 

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Explorer
Explorer
1,513 Views
Registered: ‎07-18-2018

Re: Maximum Frequency limits for FPGA from the oscillator

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@anushakodimela,

The 333Mhz and 311Mhz limits per the UG for the Clock networks means that you can't drive anything across the chip above those frequencies. It's effectivley the speed limit of the device. There doesn't appear to be things like BUFRs or BUFH's in the Spartan 3 family that might allow regionally faster clocking. So if you bring in a 50mhz signal, or a 300Mhz signal, the chip isn't going to run any faster. The DLL lets you bring in a slower frequency, and use it faster within the device.

I don't know the details of the routing on Spartan 3's but if might be possible to drive through an IO buffer some logic directly faster. But even if there is a route to drive the FF's faster with an offchip clock, the setup and hold requirments for FF's don't appear to allow for a 1000Mhz switching.

Likely the fastest you can count on a Spartan 3 device is 333Mhz regardless of what the clock on the board is doing.

@drjohnsmithgave the suggestion i was going to make, which is you can possibly have a few versions of the clock counting with a known phase offset. Such that based on when it gets counted you know when the signal arrived. So you wouldn't be able to measure a 1000mhz signal, but you might be able to get percision on where the edge of a signal appeared. Which if that's what you are interested in, might be a soultion.

 

 

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: Maximum Frequency limits for FPGA from the oscillator

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If your feeding the clock direct in, then the speed is set by your logic design, and no minimum.
If like most do, your using the DLL/ PLL / MMCM, its called different things in different chips, but for you they all do the same,
you have a max and minimum set by the block your using , which is in the data sheets,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Explorer
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Registered: ‎07-18-2018

Re: Maximum Frequency limits for FPGA from the oscillator

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@anushakodimela,

    So it looks like it depends on what you are doing with the clock, and what version of the chip you have:

So in the last DS I could find: https://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

The Clock Buffers Max speeds are 333Mhz(-5) and 311Mhz (-4)

BUFFER.PNG

The CLBs themselves:

CLB FREQ.PNG

(Which I am not certain why it's defined in Mhz)

 

And for the DLL/DCM:

3E_speed.PNG

Which should give enough information to know how fast you could drive a clock input into the chip, and how fast various elements on the chip can run. Search the UG for MHZ and it has other elements like RAMs or configuration as well.

It seems that the max speed is about 300Mhz for the fabric, and either 90, or also to almost 300Mhz for clock inputs if they need to go into the DLL.

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Observer anushakodimela
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Registered: ‎02-14-2019

Re: Maximum Frequency limits for FPGA from the oscillator

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Thanks for the quick reply evant_nq.

My requirement is very simple its just building a counter which should do the counts so fast(1 for every 1ns) .Hence required a fastest clock.We actually wanted the clock speed of 1Ghz which might not be possible with the existing oscillator present on the development board(Nexys2/Basys2) hence thinking of using a second osciallator with high frequency to drive the board.

Could you please suggest ?

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: Maximum Frequency limits for FPGA from the oscillator

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use the on chip dll / dcm to mutliply te external clock to the fpga clock you want.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Observer anushakodimela
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Registered: ‎02-14-2019

Re: Maximum Frequency limits for FPGA from the oscillator

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The count has to happen in real time without being delayed by other factors.

We are just looking to have a clock that counts the fastest as possible.

In my case the clock given to the second oscillator of the Spartan 3E FPGA has to be near to 1Ghz so that it counts for every 1ns.

In short the input for my counter module has to be close to 1Ghz.

The reason for choosing Nexys2 or basys2 with spartan 3e fpga is becuase that board has a second oscillator socket for user defined requirment and we want to use it for the oscillator that produces the highest clock and make sure that for the highest clock given the fpga should not have any limitations with the max frequency being fed.That was the main reason for asking the question regarding the frequency limits for spartan 3E .

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Historian
Historian
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Registered: ‎01-23-2009

Re: Maximum Frequency limits for FPGA from the oscillator

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Regardless of how you bring the clock in, the Spartan-3e (or for that matter any modern Xilinx FPGA) cannot run at this frequency - even for a simple counter. Again, regardless of the clock input path, a clock must be on a clock buffer in order to clock logic. The maximum clock rate of the clock buffer determines the absolute maximum frequency you can use for internal logic - this is below 1GHz in all families, and WAY below it in Spartan3e (333MHz in the fastest speed grade).

So tell us what you are trying to do - the solution of "have a counter at 1GHz" simply won't work, so you need to find a different way of doing what you are trying to do...

Avrum

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Observer anushakodimela
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Registered: ‎02-14-2019

Re: Maximum Frequency limits for FPGA from the oscillator

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That's what we figured out and want to use a second oscillator soldered into Digilent nexys board which generates a clock Input of 310Mhz to the counter .

I also have a question when Spartan 3E has 333MHz in the fastest speed grade does that mean if I have to use a clock multiplier inside before I give it to the counter(which exceeds >333Mhz) would also not work right?

For example I have a 50Mhz clock given to a multiplier 50*7=350 Mhz(>333Mhz) given to a counter is deviating from the spec ??

Thanks and Regards

Anusha Kodimela

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Historian
Historian
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Registered: ‎01-23-2009

Re: Maximum Frequency limits for FPGA from the oscillator

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All FPGAs have on-chip frequency generation capability. It is for this reason that most boards only have one (or a small number) of oscillators. If you really want to generate a 333MHz clock, you can do it in most technologies (with varying accuracy and quality) on any FPGA, regardless of the frequency of the oscillator on the board.

In all newer technologies (Spartan-6, Virtex-6, 7 series, UltraScale/UltraScale+) all devices have on-chip PLL and/or MMCM devices. These are frequency generating devices and can easily generate high quality clocks of pretty much any frequency from any on board oscillator - so, for example, any Kintex-7 board can generate a clock at or close to the maximum BUFG frequency of (lets use a -2 part as an example) 710MHz, regardless of the input oscillator (most boards have 200MHz).

On the Spartan-3e, the clock modifying block is the DCM, which is more limited, but even It can do clock multiplication and division. For example, I am pretty sure you can get 333MHz from the DCM with a 50MHz input by programming CLKFX_MULTIPLY=20 and CLKFX_DIVIDE=3 (which are both in the legal ranges of the DCM)...

So you don't need the second external oscillator to get the frequency you want...

That being said, trying to accomplish anything useful at the maximum allowable frequency of a family of FPGAs is very very hard. While the clock will run at 333MHz, designing a circuit that will run at this frequency is going to be very difficult, and if the complexity is high enough, even impossible. Simply doing a wide counter at this frequency will have a limit in terms of the number of bits - I don't know what that is, but it could be less than 32 bits (or not - one would have to try and design it).

Again, what are you trying to do? It sounds like you are trying to get some high level of timing precision - you are not trying to use the high speed clock for high throughput. If so, there may be other ways (particularly in other technologies) for accomplishing what you need (that don't involve having counters running at extremely high speeds).

Avrum

Observer anushakodimela
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Registered: ‎02-14-2019

Re: Maximum Frequency limits for FPGA from the oscillator

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We actually wanted to measure Time taken for a pulse.

So my FPGA counter would start and stop based on the the input given to the FPGA from the external source when to start and stop and does the counting.Since the start and stop would be in real time in ns we are looking for an FPGA which can serve our purpose of measuring the time.

I understand that using multipliers and dividers you can increase count speed but does not define the resolution of our system(as per our requirement).We are looking for the system clock itself to be higher as possible since kintex 7 has 200 Mhz we wanted to try frequency more than that.

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Historian
Historian
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Registered: ‎01-23-2009

Re: Maximum Frequency limits for FPGA from the oscillator

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I understand that using multipliers and dividers you can increase count speed but does not define the resolution of our system(as per our requirement).

I don't understand what you are saying here. The resolution of a counter (and, again, I am not saying this is the way to go) is the frequency of the clock. It doesn't matter if the clock in question comes directly from an oscillator, or is generated internally in a clock modifying block; the precision of a 333MHz clock is 3ns, regardless of whether that 333MHz comes from a 333MHz oscillator on the board, or a 333MHz clock generated by a DCM doing frequency multiplication and division from a 50MHz oscillator.

Now, back to your problem. If you really want to measure "time of flight" you do need a fast sampling rate, but there are other ways of doing this. For example in a 7 series device you can use a lower internal clock speed (say 200MHz) and use the ISERDES to take 1600Msamples per second using an 800MHz I/O clock using DDR clocking  with the ISERDES operating in 8:1 deserialization mode. This requires some specific clocking (using the BUFIO), but allows very high precision without having any internal counter running at ridiculous speeds.

The design here is a bit more complicated (since you need to convert wide words to effective sampling times), and there will be some imprecision due to metastability, but this is far more implementable than trying to get a counter running at the maximum fabric speed of the FPGA.

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Maximum Frequency limits for FPGA from the oscillator

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The other trick I have used, is to use the mutli phase clock,
instead of using say one counter at 100 MHz , use say 10 at 100 MHz. all phase shifted on each other.
counters run constantly,
Start / stop is used to grab the counter values at that moment,
then some number crunching needed, as you now have 10 'times', some will be one longer than the others,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Explorer
Explorer
1,514 Views
Registered: ‎07-18-2018

Re: Maximum Frequency limits for FPGA from the oscillator

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@anushakodimela,

The 333Mhz and 311Mhz limits per the UG for the Clock networks means that you can't drive anything across the chip above those frequencies. It's effectivley the speed limit of the device. There doesn't appear to be things like BUFRs or BUFH's in the Spartan 3 family that might allow regionally faster clocking. So if you bring in a 50mhz signal, or a 300Mhz signal, the chip isn't going to run any faster. The DLL lets you bring in a slower frequency, and use it faster within the device.

I don't know the details of the routing on Spartan 3's but if might be possible to drive through an IO buffer some logic directly faster. But even if there is a route to drive the FF's faster with an offchip clock, the setup and hold requirments for FF's don't appear to allow for a 1000Mhz switching.

Likely the fastest you can count on a Spartan 3 device is 333Mhz regardless of what the clock on the board is doing.

@drjohnsmithgave the suggestion i was going to make, which is you can possibly have a few versions of the clock counting with a known phase offset. Such that based on when it gets counted you know when the signal arrived. So you wouldn't be able to measure a 1000mhz signal, but you might be able to get percision on where the edge of a signal appeared. Which if that's what you are interested in, might be a soultion.

 

 

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