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Adventurer
Adventurer
4,039 Views
Registered: ‎12-30-2015

NET partially routed. How to solve it?

Hi,

 

I'm currently trying to build a clock tree which is:

 

CLKAp

 

CLKAn 

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2 Replies
Moderator
Moderator
4,034 Views
Registered: ‎01-16-2013

Re: NET partially routed. How to solve it?

@timoteo.gbm


Can you please elaborate more on the query? I assume the nets are differential pairs which needs IBUFDS.

Please check the following link:

https://forums.xilinx.com/t5/Virtex-Family-FPGAs/How-to-use-IBUFDS-OBUFDS-differential-signals-buffers-for-Virtex/td-p/63576

 

https://forums.xilinx.com/t5/Implementation/Single-Ended-Clocks-and-P-N-pair/td-p/378713

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Adventurer
Adventurer
4,014 Views
Registered: ‎12-30-2015

Re: NET partially routed. How to solve it?

This post is a mistake, it's been elaborated already. I will delete this one, otherwise, please just delete it.
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