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Observer imb29
Observer
608 Views
Registered: ‎02-14-2018

Nexys 4 DDR board, Access DDR2 refresh time and read out bitstream

Hi all, 

 

I am currently working with a Nexys 4 DDR board with DDR2 memory. I would like to be able to access and change the refresh cycle to be long enough so I can read out the bitstream after I have written all bits to a HIGH state. I have figured out how to setup an ip block with the microblaze processor and can get a bitstream to generate. When loading the SDK for the project and simply trying to use xl_printf to print Hello World over UART I get an error saying that the microblaze processor is stuck in reset. I don't know if I even need to be implementing a software layer for this projects goal, but that is what I am familiar with. I have attached a screenshot of my IP block design. I have looked at my reset lines that are tied and all are matching polarity for each, such as Active Low or Active High. Please let me know if anyone has experience in accessing the SDRAM and writing/reading it's contents. Thanks for your time and I look forward to any help!

IP_BLOCK_SDRAM_TEST.PNG
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6 Replies
Mentor watari
Mentor
602 Views
Registered: ‎06-16-2013

Re: Nexys 4 DDR board, Access DDR2 refresh time and read out bitstream

Hi @imb29

 

It seems clock issue or reset logic issue.

So, I suggest to makre sure the followings.

 

- Clock connectin on Processor System Reset module

- System clock (Active or not)

 

Best regards,

 

 

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Observer imb29
Observer
595 Views
Registered: ‎02-14-2018

Re: Nexys 4 DDR board, Access DDR2 refresh time and read out bitstream

Hi @watari

 

I will look into that. In the meantime do you have any ideas on how to help with accessing the SDRAM refresh rate so I can change it and also write/read from it? 

 

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Mentor watari
Mentor
590 Views
Registered: ‎06-16-2013

Re: Nexys 4 DDR board, Access DDR2 refresh time and read out bitstream

Hi @imb29

 

Sorry I can not understand what you want to know.

 

Here is DRAM initialize sequence and so on.

 

- DRAM initialize sequence (Automatically execute it in MIG)

- Issue refresh command with some interval

- Can issue read or write command

 

In this case, if you want to change refresh cycle from 7.8[us] to 3.9[us], my suggestio is yes.

 

However, as I already mentioned before, this issue seems clock issue on Processor System Reset.

I suggest to read the document of Processor System Reset IP.

 

Best regards,

 

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Observer imb29
Observer
587 Views
Registered: ‎02-14-2018

Re: Nexys 4 DDR board, Access DDR2 refresh time and read out bitstream

@watari

 

 

UPDATE: 

I have looked into the reset states on both system resets and one is active high and the other is active low. This was set automatically and I can not change it. The IP validates.

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Mentor watari
Mentor
578 Views
Registered: ‎06-16-2013

Re: Nexys 4 DDR board, Access DDR2 refresh time and read out bitstream

Hi @imb29

 

This IP requests input clock for synchronized reset signal.

However your design seems clock is stable.

 

Would you make sure this point ? For example, do simulation...

 

Best regards,

 

 

 

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Observer imb29
Observer
570 Views
Registered: ‎02-14-2018

Re: Nexys 4 DDR board, Access DDR2 refresh time and read out bitstream

@watari

 

I have ran simulation. My reset value is Z and I don't see a clk value. With that being said I have added a clock wizard ip to the design and ran another simulation. Now the sys_clock also had a value of Z. I am able to force a clock signal. 

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