10-09-2018 03:57 PM
I am currently working with a Nexys 4 DDR board with DDR2 memory. I would like to be able to access and change the refresh cycle to be long enough so I can read out the bitstream after I have written all bits to a HIGH state. I have figured out how to setup an ip block with the microblaze processor and can get a bitstream to generate. When loading the SDK for the project and simply trying to use xl_printf to print Hello World over UART I get an error saying that the microblaze processor is stuck in reset. I don't know if I even need to be implementing a software layer for this projects goal, but that is what I am familiar with. I have attached a screenshot of my IP block design. I have looked at my reset lines that are tied and all are matching polarity for each, such as Active Low or Active High. Please let me know if anyone has experience in accessing the SDRAM and writing/reading it's contents. Thanks for your time and I look forward to any help!
10-09-2018 04:09 PM
10-09-2018 04:17 PM - edited 10-09-2018 04:38 PM
10-09-2018 04:26 PM
Sorry I can not understand what you want to know.
Here is DRAM initialize sequence and so on.
- DRAM initialize sequence (Automatically execute it in MIG)
- Issue refresh command with some interval
- Can issue read or write command
In this case, if you want to change refresh cycle from 7.8[us] to 3.9[us], my suggestio is yes.
However, as I already mentioned before, this issue seems clock issue on Processor System Reset.
I suggest to read the document of Processor System Reset IP.
10-09-2018 04:39 PM
10-09-2018 04:59 PM
10-09-2018 05:40 PM
I have ran simulation. My reset value is Z and I don't see a clk value. With that being said I have added a clock wizard ip to the design and ran another simulation. Now the sys_clock also had a value of Z. I am able to force a clock signal.