03-25-2021 11:36 PM
I developed an LVDS input board using xc7k160t-2ffg676 device.
However, there is often a defect in the bank to which the LVDS is connected. (2.5V Bank12, 13, 14)
Data is noisy or data is not received at all.
LVDS is output from the THC63LVD device. And TVS diode is connected to LVDS output terminal.
When I checked the data with the oscilloscope, I found that there was no problem with the voltage value.
In what case does this issue occur?
04-16-2021 04:48 AM
How is the input LVDS constrained? How much timing margin are you seeing on the path?
Have you done an IBIS simulation of the path? Can you share what the simulation of the path looks like?
Can you also share the scope shot of what the input to the FPGA looks like?
04-19-2021 09:32 PM
The problem I have seems to be a physical problem.
Only 20% of the boards produced were defective.
When FPGA is replaced with a new product, the LVDS data is normal.
Is there an example of a protection schematic for the LVDS input?