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Explorer
Explorer
258 Views
Registered: ‎02-04-2013

OSERDESE2 tristate control

Hello everybody,

I would like to control the IOBUFDS through the OSERDESE2. As i understand it, i can controll it throug the OSERDESE2-T1 input. When i simulate the design the OSERDESE2-TQ is always high, not affected by the OSERDESE2-T1 input. So i cannot send any data through the IOBUFDS,

Does anybdy have an idea what is the problem with my design. This is the Artix7 fpga.

Regards

Klemen

 

 

P1_IOBUFDS_inst : IOBUFDS
generic map ( DIFF_TERM => TRUE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "BLVDS_25", SLEW => "SLOW")
port map (O => P1_in(i), IO => P1_P(i), IOB => P1_N(i), I => P1_out(i), T => P1_dir_oser(i) -- T=0:output, T=1:tristate/input
);

P1_OSERDESE2_inst : OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",-- DDR, SDR
DATA_RATE_TQ => "DDR",-- DDR, BUF, SDR
DATA_WIDTH => 8,-- Parallel data width (2-8,10,14)
INIT_OQ => '0',-- Initial value of OQ output (1'b0,1'b1)
INIT_TQ => '1',-- Initial value of TQ output (1'b0,1'b1) -- 1: input
SERDES_MODE => "MASTER", -- MASTER, SLAVE
SRVAL_OQ => '0',-- OQ output value when SR is used (1'b0,1'b1)
SRVAL_TQ => '1',-- TQ output value when SR is used (1'b0,1'b1)
TBYTE_CTL => "FALSE",-- Enable tristate byte operation (FALSE, TRUE)
TBYTE_src=> "FALSE",-- Tristate byte source (FALSE, TRUE)
TRISTATE_WIDTH => 1-- 3-state converter width (1,4)
)
port map (
OFB => open,-- 1-bit output: Feedback path for data
OQ => P1_out(i),-- 1-bit output: Data path output
-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TBYTEOUT => open,-- 1-bit output: Byte group tristate
TFB => open,-- 1-bit output: 3-state control
TQ => P1_dir_oser(i),-- 1-bit output: 3-state control
CLK => clk_serdese,-- 1-bit input: High speed clock
CLKDIV => clk,-- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => P1_Qout(i)(0),
D2 => P1_Qout(i)(1),
D3 => P1_Qout(i)(2),
D4 => P1_Qout(i)(3),
D5 => P1_Qout(i)(4),
D6 => P1_Qout(i)(5),
D7 => P1_Qout(i)(6),
D8 => P1_Qout(i)(7),
OCE => '1', -- OCE,-- 1-bit input: Output data clock enable
RST => reset, --RST,-- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => '0', --SHIFTIN1,
SHIFTIN2 => '0', --SHIFTIN2,
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => P1_dir(i),
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0',-- 1-bit input: Byte group tristate
TCE => '0'-- 1-bit input: 3-state clock enable
);

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4 Replies
Teacher drjohnsmith
Teacher
238 Views
Registered: ‎07-09-2009

Re: OSERDESE2 tristate control

dont know,
without the rest of the code , we can but guess .
but have you tried P1_dir_oser high instead of low ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Explorer
Explorer
219 Views
Registered: ‎02-04-2013

Re: OSERDESE2 tristate control

Thank you for your reply,

The P1_dir_oser signal (that drives the IOBUFDS-T input) cannot be controlled directly - i tried it, but vivado reported an error. As i understand it, it can be controlled only indirectly via OSERDES2 - i made that connection.

There is not much code

P1_Qout(i) <= "00110011"; -- to generate a clock

P1_dir(i) <= '0'; -- i thought this signal will be reflected on the P1_dir_oser. I tried low and high, but the P1_dir_oser is always high.

Regards

Klemen

 

 

 

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Explorer
Explorer
175 Views
Registered: ‎02-04-2013

Re: OSERDESE2 tristate control

This is the message you will get from vivado if you try to control the 'T' pin directly:

[Place 30-608] If the OSERDESE2 is used for 3-State Parallel-to-Serial Conversion, the 'T' pin of 3-state control buffer should be tied to 'TQ' pin of OSERDESE2. Otherwise it would lead to unroutable situation.

This is what i did, but now i cant change the state of the 'TQ' pin.

Regards

Explorer
Explorer
69 Views
Registered: ‎02-04-2013

Re: OSERDESE2 tristate control

Let me answer to myself :) 

I set the DATA_RATE_TQ => "BUF" and than it worked as i expected.

 

Regards

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