Output jitter. Excluding PLL

[ken_run]

Use the high precision external PLL to operate the ADC.
Please tell me about jitter occurring in the FPGA.
The FPGA is Vertex - 6(XC6VLX75T-XFFG784C).

[pthakare]

Hi @ken_run

What is the maximum allowable jitter value in order ADC to Digitize properly ? 

If i presume correctly , you want to use the clock Synthesized in the FPGA as ADC sampling clock ?

If so the pk-pk jitter values and phase error for each output clock from MMCM/PLL can be seen in Summary tab of Clocking Wizard IP.

Again this values are guaranteed only if VCCINT supply is noise and ripple free or within the specs.

Please elaborate on your requirement further to assist you better here.

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[ken_run]

Thank you very much. It was very helpful.

[markg@prosensing.com]

@ken_run

As you've probably concluded from information given by pthakare, using an FPGA-generated clock for the main-clock of an ADC is not recommended because jitter on the FPGA clock could significantly degrade the ADC Effective Number Of Bits (ENOB). 

However, sometimes (eg. when the board is already made) we are stuck with using the FPGA-generated clock and must make the best of it.  This is discussed and test results are given in <this> post.

Mark