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Observer ego
Observer
1,116 Views
Registered: ‎05-02-2018

PL to PL data transfer

Hi,

I would like to transfer data from one PL to another PL. I would like to know the best approach for this purpose. I am aware that it may be possible to use a bram in standalone mode. However I did not find any example about it. I would like to know if it would be a stable mode of operation if I use bram in standalone mode. More explicity I would be using different clocks for write ( from one PL) and read (from the other PL) sequences hence does this lead to any data corruption or other adverse effects?

Thanks in advance.

Engin

 

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7 Replies
Scholar drjohnsmith
Scholar
1,083 Views
Registered: ‎07-09-2009

Re: PL to PL data transfer

Do you mean Pl ?

 

Pl is the FPGA side of the chip,

    user programmable, logic design. So PL to PL is a unusual question.

 

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Observer ego
Observer
1,077 Views
Registered: ‎05-02-2018

Re: PL to PL data transfer

Actually I believe it is a very critical question. If I am not able to directly share data between two PL units how can someone realize reasonable programming on FPGA without the intervention of PS. If I need PS to transfer data between two PL, it would not be efficient.

 

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1,011 Views
Registered: ‎06-21-2017

Re: PL to PL data transfer

It is critical that it be done correctly, but it is an unusual question because you can program the PL to do (almost) anything you want. 

 

Do your FPGAs have a common clock source?  What is the rate of your data transfer?  Is the transfer bi-directional or unidirectional?  Do you want to use the AXI format, or something else?  How many signal lines do you have, that is do you want a parallel bus or a serial link?

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Observer ego
Observer
992 Views
Registered: ‎05-02-2018

Re: PL to PL data transfer

The first PL is a verilog unit operating at 3MHz, The other PL which I want to transfer data is a HLS unit which works at 100MHz. The data transfer would be unidirectional namely from the first PL to HLS. Note that I would like to have PL to PL transfer with no  PS intervention. I believe serial link is more feasible since there will be a BRAM which is accessible one at a time.

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Community Manager
Community Manager
981 Views
Registered: ‎07-23-2012

Re: PL to PL data transfer

What would be the master in your case that initiates the transfer from BRAM on FPGA0 to HLS IP on FPGA1? This can be done without a processor but you should have the relevant code to initiate the transfer.
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Observer ego
Observer
976 Views
Registered: ‎05-02-2018

Re: PL to PL data transfer

Please note that there are no two FPGAs. Both PL are on the same FPGA. BRAM may be in standalone mode, dual port setting . I am not sure about the master and hope that this should be taken care of the BRAM generator.

 

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Scholar drjohnsmith
Scholar
965 Views
Registered: ‎07-09-2009

Re: PL to PL data transfer

I have feeling your approaching this from the perspective of  software engineering,

 

PL is a Hardware design environment,

 

What you calling a PL, is in fact a design entity, 

    and multiple design entities are combined into the Pl to make the complete 

 

In terms of software, think of them a 'functions'.

    ( OK hardware people dont shout at us )

 

In software, no matter how many functions you have, a function is no use on its own, you have to wrap around it other code.

    in hardware , its the same,

 

You need to look at the IO interface of the blocks you have,

   and what format they are in , and what tools you have to combine them,

 

 

 

 

 

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