cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
489 Views
Registered: ‎02-10-2019

PL to PS add a RX only loop to xaxidma_example_sg_poll.c

Jump to solution

Dear Reader,

I am testing Zynq7 for an application that needs to transfer 48 MB/s from PL to PS.  I started with this walkthru:
> http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

The walkthru develops the IP with "AXI4-Stream Data FIFO" - "AXI DMA" - AXI_SMC to the PS S_AXI_HP0 port.  The data streams are loopback - data Written by the PS to FIFO can be Read from the FIFO and compared.  That project builds and is run from the SDK.  It passes this test software:
> C:\Xilinx\SDK\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_9\examples\xaxidma_example_sg_poll.c

I have modified that program for PL-PS
> Replaced the FIFO input with PL and can drive data into the FIFO
> Commented the TX parts in the program
> PS program waits for packet, then reports it when sent, with the right contents

However, when I run the program a 2nd time it immediatly returns the packet that had already been read.  Similarly if I add a loop in the program it continues to reports the same packet, finds no packet, etc (depending on where I put the loop).

I then went back to the original program (with Tx and Rx) and I am getting the same packet problems.

Any clues or examples would be appreciated, how to:
(a) Discard a packet once it is read
(b) Loop through multiple packets
Or maybe I need a different example to work from?

Thanks,
Dave

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer
Observer
404 Views
Registered: ‎02-10-2019

The multiple data were caused by "tvalid" being active for multiple clock ticks.

This page can be merged with an adapted version of the walkthru above and is a simpler C code base that loops through multiple packets (simple_dma.xpr.zip):
> https://www.xilinx.com/support/answers/57561.html
SG (Scatter Gather) needs to be disabled in the DMA configuration.

UG1037, starting at page 84 has good timing diagrams showing the signals of interest.  The "tvalid" and "tlast" signals provide fast and flexible options for clocking the FIFO.

I couldn't find any documentain for the "AXI4-Stream Data FIFO (2.0)" IP in Vivado 2019.1.  The Vivado link to the documentation produces an error (see below), then opens the v (3.0) documentation.

 

View solution in original post

VivadoError.jpg
0 Kudos
2 Replies
Highlighted
Observer
Observer
414 Views
Registered: ‎02-10-2019

I have made some progress.  This completed project can be combined with the WalkThru above to create a project that correctly loops through many TX and RX loopback cycles.
> https://www.xilinx.com/support/answers/57561.html (simple_dma.xpr.zip)

When I replace the FIFO input with a PL stream (instead of the outgoing stream from the PS) I can get data transfers, with varying results (no packet, one packet then hang, endless repeat of the same packet, report same packet twice and properly wait for the next packet).  It appears the results are dependent on the relative timing of these PL - FIFO signals:
> s_axis_tdata
> s_axis_tlast
> s_axis_tvalid
< s_axis_tready
PL clock is at running 100 MHz.

The best results are that the FIFO>DMA>SMC>PS reports each packet twice and then wait for the next.

I can provide (lots) more details, I am hoping someone has navigated the PL - AXI4 FIFO path and:
(a) Knows how to correct the "report each packet twice" symptom
(b) Can reference documentation or diagram that shows the correct timing relationships of the FIFO signals
(c) Has some other ideas

Thanks,
Dave

 

 

0 Kudos
Highlighted
Observer
Observer
405 Views
Registered: ‎02-10-2019

The multiple data were caused by "tvalid" being active for multiple clock ticks.

This page can be merged with an adapted version of the walkthru above and is a simpler C code base that loops through multiple packets (simple_dma.xpr.zip):
> https://www.xilinx.com/support/answers/57561.html
SG (Scatter Gather) needs to be disabled in the DMA configuration.

UG1037, starting at page 84 has good timing diagrams showing the signals of interest.  The "tvalid" and "tlast" signals provide fast and flexible options for clocking the FIFO.

I couldn't find any documentain for the "AXI4-Stream Data FIFO (2.0)" IP in Vivado 2019.1.  The Vivado link to the documentation produces an error (see below), then opens the v (3.0) documentation.

 

View solution in original post

VivadoError.jpg
0 Kudos