cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
davecowl
Visitor
Visitor
11,477 Views
Registered: ‎08-26-2011

PUDC floating on Kintex XC7K160T - what will happen?

Jump to solution

I have a design for the Kintex 7 in the FFG676 package and it has come to my attention since creating the design that the PUDC pin wants to be tied high or low.

 

While on one design the pin is used, on another it is NC and therefore will have no access once the board is assembled.

 

What will happen if this pin floats? Will it never configure?

 

Is it worth scrapping the boards before they are assembled?

 

I need to know how big a problem this is and what if anything can or should be done to the board to fix it during assembly etc...

 

Cheers! Dave.

0 Kudos
1 Solution

Accepted Solutions
ralfk
Xilinx Employee
Xilinx Employee
15,182 Views
Registered: ‎10-11-2007

PUDC_B determines if the FPGA pins are pulled up or not. The PUDC_B pin itself is subject to that. So if it's left floating then it may turn on and off cyclically the weak pullups. Oscillating PULLUPs (PULLUPs being turned on/off cyclically) on user I/O during configuration may not be a good idea for some applications. But if you don’t care then there won’t be any other issues.

View solution in original post

0 Kudos
13 Replies
ralfk
Xilinx Employee
Xilinx Employee
15,183 Views
Registered: ‎10-11-2007

PUDC_B determines if the FPGA pins are pulled up or not. The PUDC_B pin itself is subject to that. So if it's left floating then it may turn on and off cyclically the weak pullups. Oscillating PULLUPs (PULLUPs being turned on/off cyclically) on user I/O during configuration may not be a good idea for some applications. But if you don’t care then there won’t be any other issues.

View solution in original post

0 Kudos
davecowl
Visitor
Visitor
11,472 Views
Registered: ‎08-26-2011

Ok thanks. I could see that...

 

I am mostly concerned with the possibility of it messing up the configuration process.

 

If it won't have a negative effect on that I think we will be ok.

 

Cheers!

0 Kudos
davecowl
Visitor
Visitor
11,471 Views
Registered: ‎08-26-2011
It is intriguing to think that it is active low. If it was active high, it would potentially set itself and stay set! :D
0 Kudos
gszakacs
Instructor
Instructor
11,466 Views
Registered: ‎08-14-2007

@ralfk wrote:

PUDC_B determines if the FPGA pins are pulled up or not. The PUDC_B pin itself is subject to that. So if it's left floating then it may turn on and off cyclically the weak pullups. Oscillating PULLUPs (PULLUPs being turned on/off cyclically) on user I/O during configuration may not be a good idea for some applications. But if you don’t care then there won’t be any other issues.


This is probably why earlier devices had a pullup enabled on the PUDC_B (or HSWAP_EN) pin that didn't depend on the setting of the pin itself.  Strange that Xilinx changed this in going to 7-series.

-- Gabor
0 Kudos
ralfk
Xilinx Employee
Xilinx Employee
11,447 Views
Registered: ‎10-11-2007

Configuration will be fine.

0 Kudos
lamurphy1
Newbie
Newbie
11,202 Views
Registered: ‎01-02-2014

So, I am having trouble configuring the XC7K160T, using SPIx1 configuration, with the PUDC_B line left floating. Are you saying that it would not have to do with the state of the PUDC_B line during configuration?

0 Kudos
mcgett
Xilinx Employee
Xilinx Employee
11,197 Views
Registered: ‎01-03-2008

A floating PUDC_B pin can cause problems as documented in the 7 Series Configuration User Guide UG470.

 

PUDC_B must be tied either directly, or via a 1 kΩ (or stronger) resistor, to VCCO_14 or GND.
Caution! Do not allow this pin to float before and during configuration.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
lamurphy1
Newbie
Newbie
11,171 Views
Registered: ‎01-02-2014

We have built a board with the PUDC_B line left floating and no way to get to it. The FPGA will not program via the JTAG lines. Would it be possible to add pullups to some the lines that we have access to (like JTAG)  in order to get the FPGA to program or did we just build a "throw-away" board. Is there any kind of a work around for leaving the PUDC_B line floating?

0 Kudos
mcgett
Xilinx Employee
Xilinx Employee
11,167 Views
Registered: ‎01-03-2008

What errors are you getting when programming by JTAG?  Do you have external resistors on the M[2:0] pins?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
lamurphy1
Newbie
Newbie
6,119 Views
Registered: ‎01-02-2014

We are trying to program just the FPGA and get a "Program Failed" error. We cannot read the device ID code or anything, M0_0 is tied directly to 3.3V while the other two are grounded. I know that this is the mode for Master SPI1 but we cannot change those either. The device may not be JTAG programmable (FPGA alone) just because of the state of our mode pins.

0 Kudos
mcgett
Xilinx Employee
Xilinx Employee
6,114 Views
Registered: ‎01-03-2008

> We cannot read the device ID code or anything,

 

This is unlikely an issue with PUDC_B and is far more likely that you have a problem with the JTAG chain.  You need to get out a scope and probe the TCK and TDO pins of the FPGA and any TDI/TDO points from the FPGA to the JTAG cable to determine where it is broken.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
jthibeault
Newbie
Newbie
6,011 Views
Registered: ‎03-18-2014

The configuration guide states that the PUDC_B signal must be pulled high or low in the UG470 Configuration guide, however there is no note on what will actually happen if this pin is left floating. Can we can get definatitive information on what may happen if this pin is left floating?

0 Kudos
mcgett
Xilinx Employee
Xilinx Employee
6,002 Views
Registered: ‎01-03-2008

If you leave the pin floating it will result in alternating PULLUPs/no-PULLUps on the I/O pins until the end of configuration and this is generally a bad thing.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos