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Observer dylan.campbell
Observer
436 Views
Registered: ‎08-31-2018

ParHelpers: 360 - Design is not completely routed - OSERDES2 to ODDR

Hello all,

I'm getting the 'design is not completely routed error' on a design I'm working on.  I'm trying to create a simple 10:1 serializer using a Spartan 6.  The way I'm doing this is by creating 2 5:1 serializers and feeding the output of those to an ODDR.  I'm getting an error that says the signals between the output of the OSERDES2 and the input of the ODDR is unroutable.  I can't seem to find out why.  I've looked at a few of the other topics with this problem but none of them seem to have my problem.  I have my clock given to a BUFG which I saw was a common problem. 

The problem signals are:

   blueSer/evenData
   blueSer/oddData
   greenSer/evenData
   greenSer/oddData
   redSer/evenData
   redSer/oddData
   serStrobeSR_2

And the code is:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    06:11:45 01/09/2019 
// Design Name: 
// Module Name:    Ser_10_1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Ser_10_1(
   input wire parClk,
   input wire serClk,
   input wire dataStrobe,
   input wire serCE,
   input wire reset,
   input wire[9:0] parData,
   
   output serData
   );
   
   parameter integer dataWidth = 5;
   
   wire cascade_do1, cascade_do2, cascade_to1, cascade_to2;
   wire cascade_di1, cascade_di2, cascade_ti1, cascade_ti2;
   wire evenData, oddData;
   

      // Output serializer 
   OSERDES2 #(
              .DATA_RATE_OQ("SDR"),
              .DATA_RATE_OT("SDR"),
              .DATA_WIDTH(dataWidth),
              .OUTPUT_MODE("SINGLE_ENDED"),
              .SERDES_MODE("MASTER"),
              .TRAIN_PATTERN(4'hA)
              ) serdesMaster1 (
              .CLK0(serClk),
              .CLK1(),
              .CLKDIV(parClk),
              .IOCE(dataStrobe),
              .D1(parData[8]),
              .D2(1'b0),
              .D3(1'b0),
              .D4(1'b0),
              .OCE(serCE),
              .RST(~reset),
              .T1(1'b0),
              .T2(1'b0),
              .T3(1'b0),
              .T4(1'b0),
              .TCE(1'b1),
              .SHIFTIN1(1'b1),
              .SHIFTIN2(1'b1),
              .SHIFTIN3(cascade_do1),
              .SHIFTIN4(cascade_to1),
              .TRAIN(1'b0),
              .OQ(evenData),
              .TQ(),
              .SHIFTOUT1(cascade_di1),
              .SHIFTOUT2(cascade_ti1),
              .SHIFTOUT3(),
              .SHIFTOUT4()
              );

   OSERDES2 #(
              .DATA_RATE_OQ("SDR"),
              .DATA_RATE_OT("SDR"),
              .DATA_WIDTH(dataWidth),
              .OUTPUT_MODE("SINGLE_ENDED"),
              .SERDES_MODE("SLAVE"),
              .TRAIN_PATTERN(4'hA)
              ) serdesSlave1 (
              .CLK0(serClk),
              .CLK1(),
              .CLKDIV(parClk),
              .IOCE(dataStrobe),
              .D1(parData[0]),
              .D2(parData[2]),
              .D3(parData[4]),
              .D4(parData[6]),
              .OCE(serCE),
              .RST(~reset),
              .T1(1'b0),
              .T2(1'b0),
              .T3(1'b0),
              .T4(1'b0),
              .TCE(1'b1),
              .SHIFTIN1(cascade_di1),
              .SHIFTIN2(cascade_ti1),
              .SHIFTIN3(1'b1),
              .SHIFTIN4(1'b1),
              .TRAIN(1'b0),
              .OQ(),
              .TQ(),
              .SHIFTOUT1(),
              .SHIFTOUT2(),
              .SHIFTOUT3(cascade_do1),
              .SHIFTOUT4(cascade_to1)
              );

   OSERDES2 #(
              .DATA_RATE_OQ("SDR"),
              .DATA_RATE_OT("SDR"),
              .DATA_WIDTH(dataWidth),
              .OUTPUT_MODE("SINGLE_ENDED"),
              .SERDES_MODE("MASTER"),
              .TRAIN_PATTERN(4'hA)
              ) serdesMaster2 (
              .CLK0(serClk),
              .CLK1(),
              .CLKDIV(parClk),
              .IOCE(dataStrobe),
              .D1(parData[9]),
              .D2(1'b0),
              .D3(1'b0),
              .D4(1'b0),
              .OCE(serCE),
              .RST(~reset),
              .T1(1'b0),
              .T2(1'b0),
              .T3(1'b0),
              .T4(1'b0),
              .TCE(1'b1),
              .SHIFTIN1(1'b1),
              .SHIFTIN2(1'b1),
              .SHIFTIN3(cascade_do2),
              .SHIFTIN4(cascade_to2),
              .TRAIN(1'b0),
              .OQ(oddData),
              .TQ(),
              .SHIFTOUT1(cascade_di2),
              .SHIFTOUT2(cascade_ti2),
              .SHIFTOUT3(),
              .SHIFTOUT4()
              );

   OSERDES2 #(
              .DATA_RATE_OQ("SDR"),
              .DATA_RATE_OT("SDR"),
              .DATA_WIDTH(dataWidth),
              .OUTPUT_MODE("SINGLE_ENDED"),
              .SERDES_MODE("SLAVE"),
              .TRAIN_PATTERN(4'hA)
              ) serdesSlave2 (
              .CLK0(serClk),
              .CLK1(),
              .CLKDIV(parClk),
              .IOCE(dataStrobe),
              .D1(parData[1]),
              .D2(parData[3]),
              .D3(parData[5]),
              .D4(parData[7]),
              .OCE(serCE),
              .RST(~reset),
              .T1(1'b0),
              .T2(1'b0),
              .T3(1'b0),
              .T4(1'b0),
              .TCE(1'b1),
              .SHIFTIN1(cascade_di2),
              .SHIFTIN2(cascade_ti2),
              .SHIFTIN3(1'b1),
              .SHIFTIN4(1'b1),
              .TRAIN(1'b0),
              .OQ(),
              .TQ(),
              .SHIFTOUT1(),
              .SHIFTOUT2(),
              .SHIFTOUT3(cascade_do2),
              .SHIFTOUT4(cascade_to2)
              );                             
  
         
   // Output DDR 
   ODDR2 #(
            .DDR_ALIGNMENT("C0"),
            .INIT(1'b0),
            .SRTYPE("ASYNC")
            ) DDROutRed (
            .D0(evenData),
            .D1(oddData),
            .C0(serClk),
            .C1(~serClk),
            .CE(serCE),
            .R(~reset),
            .S(1'b0),
            .Q(serData)
            );

endmodule

Does anyone know why this is happening?  Or how I could get more info about why this is seen as unroutable?

Thank you,

Dylan

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3 Replies
Xilinx Employee
Xilinx Employee
429 Views
Registered: ‎06-30-2010

Re: ParHelpers: 360 - Design is not completely routed - OSERDES2 to ODDR

what is the exact error that you get?
There is no direct path to the ODDR input from the SERDES. Where are the pins placed?
Are you planning on outputting the data stream back on to the board?
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Observer dylan.campbell
Observer
404 Views
Registered: ‎08-31-2018

Re: ParHelpers: 360 - Design is not completely routed - OSERDES2 to ODDR

The exact error is:

WARNING:ParHelpers:360 - Design is not completely routed.

   blueSer/evenData
   blueSer/oddData
   greenSer/evenData
   greenSer/oddData
   redSer/evenData
   redSer/oddData
   serStrobeSR_2

 

So the the problem is just that you can't go from SERDES output to ODDR input?  I'm guessing you're intended to use the "DDR" option in the OSERDES if you want DDR?

The data is intended to leave the FPGA after the ODDR output. 

Thank you!

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Xilinx Employee
Xilinx Employee
359 Views
Registered: ‎06-30-2010

Re: ParHelpers: 360 - Design is not completely routed - OSERDES2 to ODDR

are you trying to route from the ISERDES to the ODDR in the same IOB or a different one?

You are able to go from the ISERDES to fabric and then back out via the ODDR in a separate IOB.
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