01-03-2020 04:26 AM
01-03-2020 05:33 AM
01-05-2020 08:33 PM - edited 01-06-2020 09:13 PM
Mine is an assign statement in verilog to connect one input in one bank to the output in other bank. I want to reduce the routing delay. There are no clocking elements. Every thing is purely a combinatorial even that too assign statements.
01-05-2020 10:09 PM
Pipelinening is fine when there's a clock in the design. Mine is completely combinatorial. Can anyone let me know ways to reduce 'net type' delay.
01-05-2020 10:28 PM
Would you consider the following option ?
- Register duplication
- Register balancing
- Move 1st flip flop stage
- Move last flip flop stage
- Pack I/O registers into IOBs
- Reduce control sets
- Optimize instantiated primitives
01-05-2020 11:46 PM
01-05-2020 11:49 PM
01-05-2020 11:56 PM
Hi @drjohnsmith ,
I am on very think ice here, since most of my experience on these issues comes from different FPGA vendor, but when working on these different FPGAs we used concepts of virtual clocks.
You simply defined clocks that were not existing in the design and the used these clocks to reference the constraints. I believe, that something similar could be done here. You would define clocks with some period and set min and max delays in reference to these clocks. No register between input and output only means that you would have to be able to travel whole path in one period. But i freely admit I may be completely wrong.
01-06-2020 01:21 AM
01-06-2020 03:13 AM
01-06-2020 06:12 AM
01-06-2020 08:58 AM
@markgraf gave the proper commands to constrain a combinatorial path through the FPGA in ISE. However, it is unlikely to make much of a difference; if the FPGA is empty (or near empty) then this route is probably already close to as fast as it can be. But you should still add the constraints.
You have to understand what you are asking the device to do:
So, in the end you need to realize that FPGAs aren't optimized for combinatorial paths through the FPGA - these paths are not expected to be particularly fast...