cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
xzsawq21
Observer
Observer
8,894 Views
Registered: ‎11-24-2017

Pin Assignment

Jump to solution

Hello

I have a MicroZed board based on Zynq 7020.

apart less of  the main clock source on the board I have an additional external clock source to synchronize a program separately on the FPGA. the maximun clock rate of the additional CLOCK is 65MHz.

 

the board has two PL side Bank 34 and 35 on the carrier board.

I checked the UG865 document to see SRCC and MRCC pins.

which pins of Bank 34 and 35 are SRCC and MRCC?

 

Thanks

0 Kudos
1 Solution

Accepted Solutions
klumsde
Moderator
Moderator
10,654 Views
Registered: ‎04-18-2011
If you lock your clock to one of the clock pins then it's used to route the clock into the device but all the other ccio pins in the bank are available as IO.
Also remember for single ended clocks you have to come in on the p side of the pair.
The XADC aux inputs are only reserved and not available as IO if you instantiate the XADC and set it up to sample aux channels, otherwise they are just regular IO

Yes any multi function pin can be used as an IO
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

26 Replies
klumsde
Moderator
Moderator
8,867 Views
Registered: ‎04-18-2011
Hi
So there are 2 ways to find out.
Open the ASCII pinout file and go to bank 34 or 35 and look at the pin names. They are named as MRCC or SRCC.
The other option is to open your elaborated design or open the design post synth and then you will see the clock pins in the IO planning view if you look at the package tab. In the bank the clock pins are not round they are hexagonal if you select it you can tell if it is multi region or not by it's name
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
8,856 Views
Registered: ‎11-24-2017

Dear

I downloaded the ASCII file:

https://www.xilinx.com/support/packagefiles/z7packages/xc7z020clg400pkg.txt

 

I found the Bank 34 and 35 in the list.

 

some pins are as follow:

  • general I/O (single Ended or diff pair)
  • PUDC_B (Pull-Up During Configuration)
  • SRCC or MRCC (clock capable I/Os)
  • VREF (These are input threshold voltage pins, They become user I/Os when an external threshold voltage is not needed)
  • AD0P...AD15P (XADC differential auxiliary analog inputs 0–15)
  • DQS (I think! The DDR DQS strobe pin that belongs to the memory byte group T0–T3)

 

also I found that the I/O type is HR.

 

Actually I have a high Speed 14Bit ADC and DAC.

 

  • to run the ADC I need (ADC level is 1.8V):

1 output pin to generate a 50MHz clock

30 input pins to receive the digital data from the ADC 

1 input pin to receive a clock from the ADC (this is a feedback clock, actually this clock is fully synchronized with the output data of the ADC!)

 

  • to run the DAC (DAC level is 3.3V):

1 output pin to generate 100MHz clock

14 output pins to send the digital data to the DAC.

 

which type of pins from the Bank 34/35 can I use to run above ADC and DAC?

what's the HR?

due to the level of ADC and DAC I should set the level of each Banks to 1.8V and 3.3V separately . can I do it? (on the board I can set the VCCIO)

 

Thanks

 

 

 

 

0 Kudos
klumsde
Moderator
Moderator
8,845 Views
Registered: ‎04-18-2011
Is the ADC transmitting LVDS data to the device?
If this is the case then you have a problem. There are only 50 IO in a bank... You'll have to spread it across the 2 banks.

HR means high range which means you have the extra range on the vcco it will support 2.5V and 3.3V IO.

LVDS In HR banks is called LVDS_25 vcco needs to be 2.5V for outputs and if you want an I put that uses the 100ohm on chip termination. For an input you can power the bank vcco with a voltage that is not 2.5V but diff term won't be allowed. You'll need to put the termination on the board in that case.

I would advise you to make a pin planning project and create these interfaces and place your pins in Vivado and then run a DRC to legalise this pin out...

Keith
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
8,842 Views
Registered: ‎11-24-2017

Dear

the ADC and DAC both are single ended type.

I need more help. my time is very limited bcoz I should modify the carrier board for the MicroZed to finish my thesis :'(

 

on the MicroZed board I can set the level of VCCIO for the Bank 34 and 35 to 1.8/2.5/3.3 Volts as follow

power set.PNG

 

the ADC level is 1.8V and the DAC level is 3.3V. for example if could I would set the VCCIO for the Bank 34 to 1.8V and for the Bank 35 to 3.3V.

 

I have posted more information before...

which pins of Bank34/35 can I use for my application? (there are many different types in both Banks such as DQS, AD0P, IO,...)

 

Please help me

0 Kudos
klumsde
Moderator
Moderator
8,829 Views
Registered: ‎04-18-2011
Ok then you can forget what I was saying about LVDS this is a differential IO.
SO there are 50 single ended IO in each bank. Place the ADC inputs in the 1.8V bank. Take care with the clock pins.
Then place the DAC outputs in the 3.3V bank and it's job done.

I'd still recommend you check the placement with a DRC in vivado post synthesis
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
8,818 Views
Registered: ‎11-24-2017

can I set the Banks in 1.8V mode? bcoz you said the I/O pins are HR.

about the clock, you mean I should connect the ADC's output clock to SRCC or MRCC pins?

can I connect the ADC's output clock to both SRCC and MRCC pins at the same time? now I don't know which one I will use. very soon it depends on the situation in my code I can use selected SRCC or MRCC pin. 

 

 

some pins of Banks 34 are PUDB and AD0P... as follow:

pudc.PNG

ad0p.PNG

can I use both as output pins? bcoz most of the pins in Bank35 are AD0P-AD15P and SRCC/MRCC.

 

can I connect an input or output logic to the SRCC/MRCC pins? or SRCC/MRCC are only dedicated to the Clock circuitry?

 

Thanks

0 Kudos
klumsde
Moderator
Moderator
8,808 Views
Registered: ‎04-18-2011
Hard banks can be powered with 1.8v
You need to route the clock from the ADC to a clock capable IO otherwise the tools complain because there is no direct connection to clocking infrastructure of the FPGA from other IO.
Unused ccio can be used as regular IO.
Forwarding out a clock doesn't need to use a clock capable IO...

Pudc_b is multi-function so it can be used as a normal IO post config.
The same applies to the IO that are used for the aux inputs of the XADC. If they are not being used by the XADC then they are available as regular IO
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
klumsde
Moderator
Moderator
8,807 Views
Registered: ‎04-18-2011
Sorry the should have said HR banks can be powered at 1.8v
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
8,729 Views
Registered: ‎11-24-2017

Dear

you have helped me a lot :)

1-only the SRCC and MRCC pins are CCIO. Yes?

for example if I use one SRCC pin I can not use it as a regular I/O bcoz I assigned it as a Clock pin.

 

2-You mentioned Multi-Function pins...I'm still a little puzzled :)

the pin out is as follow:

pins.PNG

Red blanket shows general Single Ended or Diff pair I/O. it's OK.

 

Blue blanket shows Multi-Function pins. you said I can use them as regular I/O if I don't assign them before. for example If don't want to use XADC all the AD0P...AD015 pins are free and I can use them as regular I/O.

if I don't use for example this SRCC pin, I can use this pin as a regular I/O.

is there a same rule for other pins in the Blue blanket?

if so now I can develop the carrier board for my MicroZed.

 

 

Best Regards

0 Kudos
klumsde
Moderator
Moderator
10,655 Views
Registered: ‎04-18-2011
If you lock your clock to one of the clock pins then it's used to route the clock into the device but all the other ccio pins in the bank are available as IO.
Also remember for single ended clocks you have to come in on the p side of the pair.
The XADC aux inputs are only reserved and not available as IO if you instantiate the XADC and set it up to sample aux channels, otherwise they are just regular IO

Yes any multi function pin can be used as an IO
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

xzsawq21
Observer
Observer
8,445 Views
Registered: ‎11-24-2017

You are a great teacher :)

wish I had a chance to learn Zynq from you :)

Thanks for your attentions and your remarks.

 

0 Kudos
xzsawq21
Observer
Observer
8,411 Views
Registered: ‎11-24-2017

Dear

I checked the below topic:

https://forums.xilinx.com/t5/7-Series-FPGAs/LVDS-in-HR-banks/td-p/206709

 

  • the DAC is completely parallel CMOS 3.3v. I want to dedicate Bank 35 to the DAC.
  • Zynq 7020 only has HR Banks, on the other hand I have only 14 pairs LVDS 1.8v to receive the digital data from the ADC and 1 pair to generate a differential clock for the ADC. I want to dedicate Bank 34 to the ADC. I think soldering 100 Ohm resistors with my hands is impossible to terminate the bus correctly.

is there any problem?

 

0 Kudos
klumsde
Moderator
Moderator
8,402 Views
Registered: ‎04-18-2011
You can't use the 100ohm on chip termination unless the bank vcco is 2.5V not can you have an LVDS output unless the bank is 2.5V. I tried to tell you this earlier but then you said the interface wasn't differential
You said there were 30 ADC channels this won't all for on the one single bank either.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
klumsde
Moderator
Moderator
8,397 Views
Registered: ‎04-18-2011
30 channels implies 30 pairs. If it is 15 pairs (30 lines then that's ok)
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
8,381 Views
Registered: ‎11-24-2017

and when I set the bank to 2.5V so I can't use LVDS 1.8v, OK?

actually the ADC supports both 1.8V CMOS or LVDS output... earlier I wanted to use the ADC in CMOS mode. I think I can not use the ADC in LVDS 1.8v mode with ZYNQ7020.

 

Thanks

0 Kudos
klumsde
Moderator
Moderator
8,375 Views
Registered: ‎04-18-2011

Hi @xzsawq21

 

there is no such thing as 1.8V or 2.5V or indeed 3.3V LVDS. In the real world it is just LVDS. Some vendors accomodate it using different VCC's

For flexibility Xilinx have 2 IO Standard LVDS for the HP bank and LVDS_25 for the HR bank. 

The LVDS_25 input can be placed in a bank with  its VCCO not equal to 2.5V as long as you can ensure that the common mode and input swing is in line with the data sheet and you don't Violate the VIN spec. 

The drawback is that you can't implement DIFF_TERM on the chip unless the bank voltage is 2.5V. Also you are talking about forwarding an LVDS clock which would mean an output and then the LVDS_25 VCCO requirement would need to be met. 

have a look here 

https://www.xilinx.com/support/answers/43989.html

 

 

Keith 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
8,369 Views
Registered: ‎11-24-2017

Dear

 

I checked the ADC's datasheet again:

 

LVDS.PNG

I think LVDS_25 in ZYNQ7020 use a 2.5V supply to support the differential signals with Vcm=1.25V and Ddm~0.3V. OK?

if I set the VCCO in 2.5V for then Bank 34 or 35, I think there is no problem with this ADC.

also when I use LVDS_25 as input I can activate the internal termination and there is no need to use external 100 ohm resistors.

0 Kudos
klumsde
Moderator
Moderator
8,360 Views
Registered: ‎04-18-2011
Sure
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
klumsde
Moderator
Moderator
8,359 Views
Registered: ‎04-18-2011
Sure, if your bank voltage is 2.5v diff_term is available.
Will there now be a problem with the DAC?
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
7,888 Views
Registered: ‎11-24-2017

I want to route the DAC in another Bank bcoz the DAC uses 3.3V CMOS interface.

both the DAC/ADC have differential/CMOS clock input.

earlier I wanted to produce a clock based on the PLL-based inside ZYNQ to feed both DAC/ADC, but now I think the jitter is not very low. I couldn't find anything about the jitter for ZYNQ.

 

Thanks

0 Kudos
xzsawq21
Observer
Observer
7,882 Views
Registered: ‎11-24-2017

...

0 Kudos
klumsde
Moderator
Moderator
7,867 Views
Registered: ‎04-18-2011

It looks like it is an Analog Devices DAC.

Can you link to the Datasheet?

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
7,846 Views
Registered: ‎11-24-2017

I have another question :)

in the Bank 34, there are 50 pins, or 25 LVDS pairs. consider I set the voltage Bank to 2.5V.

I want to dedicate 15 pairs (30 pins) to the ADC. so 20 pins still remain free. can I use free pins as regular I/O?

bcoz one of IC in my circuit needs SPI communication and some activation commands (such as Reset pin,....).

 

the SPI protocol levels are as follow:

SCLK, SDIO: minimum Level for Logic 1 is: 2.5V-0.4V=2.1V

 

for other activator pins

minimum Level for the High Level is 1.7V

 

Thanks

0 Kudos
klumsde
Moderator
Moderator
7,842 Views
Registered: ‎04-18-2011
Sure you are free to use them as lvcmos25 IO.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
xzsawq21
Observer
Observer
7,712 Views
Registered: ‎11-24-2017

I have another question.

I want to connect a LVDS clock to the ZYNQ. if I use LVDS25 for the BANK34 or 35, is the Bank internally biassed?

 

I mean, usually we can put the below filter at the input of receiver (here is FPGA) to block the DC common voltage:

30177323a.gif

 

Thanks :)

 

 

0 Kudos
gnarahar
Moderator
Moderator
7,700 Views
Registered: ‎07-23-2015

@xzsawq21 First of all, its always a good practice to post new queries in a separate thread as this thread resolved your original query. Helps your query get visibility along with helps other forum members who may have the same query. 

 

Coming to your query, No, 7-series/Zynq LVDS buffers do not have internal biasing. you will need to use external biasing circuit for AC-coupled applications. Check Figure 1-72 from UG471

 

 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------