11-24-2017 10:21 AM - edited 11-24-2017 01:01 PM
I have a MicroZed board based on Zynq 7020.
apart less of the main clock source on the board I have an additional external clock source to synchronize a program separately on the FPGA. the maximun clock rate of the additional CLOCK is 65MHz.
the board has two PL side Bank 34 and 35 on the carrier board.
I checked the UG865 document to see SRCC and MRCC pins.
which pins of Bank 34 and 35 are SRCC and MRCC?
11-25-2017 12:25 AM
11-24-2017 11:19 AM
11-24-2017 12:57 PM - edited 11-24-2017 12:58 PM
I downloaded the ASCII file:
I found the Bank 34 and 35 in the list.
some pins are as follow:
also I found that the I/O type is HR.
Actually I have a high Speed 14Bit ADC and DAC.
1 output pin to generate a 50MHz clock
30 input pins to receive the digital data from the ADC
1 input pin to receive a clock from the ADC (this is a feedback clock, actually this clock is fully synchronized with the output data of the ADC!)
1 output pin to generate 100MHz clock
14 output pins to send the digital data to the DAC.
which type of pins from the Bank 34/35 can I use to run above ADC and DAC?
what's the HR?
due to the level of ADC and DAC I should set the level of each Banks to 1.8V and 3.3V separately . can I do it? (on the board I can set the VCCIO)
11-24-2017 01:17 PM
11-24-2017 01:28 PM - edited 11-24-2017 01:34 PM
the ADC and DAC both are single ended type.
I need more help. my time is very limited bcoz I should modify the carrier board for the MicroZed to finish my thesis :'(
on the MicroZed board I can set the level of VCCIO for the Bank 34 and 35 to 1.8/2.5/3.3 Volts as follow
the ADC level is 1.8V and the DAC level is 3.3V. for example if could I would set the VCCIO for the Bank 34 to 1.8V and for the Bank 35 to 3.3V.
I have posted more information before...
which pins of Bank34/35 can I use for my application? (there are many different types in both Banks such as DQS, AD0P, IO,...)
Please help me
11-24-2017 01:39 PM
11-24-2017 02:24 PM
can I set the Banks in 1.8V mode? bcoz you said the I/O pins are HR.
about the clock, you mean I should connect the ADC's output clock to SRCC or MRCC pins?
can I connect the ADC's output clock to both SRCC and MRCC pins at the same time? now I don't know which one I will use. very soon it depends on the situation in my code I can use selected SRCC or MRCC pin.
some pins of Banks 34 are PUDB and AD0P... as follow:
can I use both as output pins? bcoz most of the pins in Bank35 are AD0P-AD15P and SRCC/MRCC.
can I connect an input or output logic to the SRCC/MRCC pins? or SRCC/MRCC are only dedicated to the Clock circuitry?
11-24-2017 03:05 PM
11-24-2017 03:06 PM
11-24-2017 11:10 PM
you have helped me a lot :)
1-only the SRCC and MRCC pins are CCIO. Yes?
for example if I use one SRCC pin I can not use it as a regular I/O bcoz I assigned it as a Clock pin.
2-You mentioned Multi-Function pins...I'm still a little puzzled :)
the pin out is as follow:
Red blanket shows general Single Ended or Diff pair I/O. it's OK.
Blue blanket shows Multi-Function pins. you said I can use them as regular I/O if I don't assign them before. for example If don't want to use XADC all the AD0P...AD015 pins are free and I can use them as regular I/O.
if I don't use for example this SRCC pin, I can use this pin as a regular I/O.
is there a same rule for other pins in the Blue blanket?
if so now I can develop the carrier board for my MicroZed.
11-25-2017 12:25 AM
11-27-2017 11:45 AM
I checked the below topic:
is there any problem?
11-27-2017 01:05 PM
11-27-2017 01:10 PM
11-27-2017 11:10 PM
and when I set the bank to 2.5V so I can't use LVDS 1.8v, OK?
actually the ADC supports both 1.8V CMOS or LVDS output... earlier I wanted to use the ADC in CMOS mode. I think I can not use the ADC in LVDS 1.8v mode with ZYNQ7020.
11-28-2017 01:07 AM
there is no such thing as 1.8V or 2.5V or indeed 3.3V LVDS. In the real world it is just LVDS. Some vendors accomodate it using different VCC's
For flexibility Xilinx have 2 IO Standard LVDS for the HP bank and LVDS_25 for the HR bank.
The LVDS_25 input can be placed in a bank with its VCCO not equal to 2.5V as long as you can ensure that the common mode and input swing is in line with the data sheet and you don't Violate the VIN spec.
The drawback is that you can't implement DIFF_TERM on the chip unless the bank voltage is 2.5V. Also you are talking about forwarding an LVDS clock which would mean an output and then the LVDS_25 VCCO requirement would need to be met.
have a look here
11-28-2017 03:41 AM - edited 11-28-2017 04:34 AM
I checked the ADC's datasheet again:
I think LVDS_25 in ZYNQ7020 use a 2.5V supply to support the differential signals with Vcm=1.25V and Ddm~0.3V. OK?
if I set the VCCO in 2.5V for then Bank 34 or 35, I think there is no problem with this ADC.
also when I use LVDS_25 as input I can activate the internal termination and there is no need to use external 100 ohm resistors.
11-28-2017 11:47 AM
11-28-2017 11:48 AM
11-28-2017 12:06 PM
I want to route the DAC in another Bank bcoz the DAC uses 3.3V CMOS interface.
both the DAC/ADC have differential/CMOS clock input.
earlier I wanted to produce a clock based on the PLL-based inside ZYNQ to feed both DAC/ADC, but now I think the jitter is not very low. I couldn't find anything about the jitter for ZYNQ.
11-29-2017 05:05 AM
It looks like it is an Analog Devices DAC.
Can you link to the Datasheet?
12-01-2017 01:45 PM
I have another question :)
in the Bank 34, there are 50 pins, or 25 LVDS pairs. consider I set the voltage Bank to 2.5V.
I want to dedicate 15 pairs (30 pins) to the ADC. so 20 pins still remain free. can I use free pins as regular I/O?
bcoz one of IC in my circuit needs SPI communication and some activation commands (such as Reset pin,....).
the SPI protocol levels are as follow:
SCLK, SDIO: minimum Level for Logic 1 is: 2.5V-0.4V=2.1V
for other activator pins
minimum Level for the High Level is 1.7V
12-01-2017 03:37 PM
12-11-2017 11:34 AM
I have another question.
I want to connect a LVDS clock to the ZYNQ. if I use LVDS25 for the BANK34 or 35, is the Bank internally biassed?
I mean, usually we can put the below filter at the input of receiver (here is FPGA) to block the DC common voltage:
12-11-2017 09:22 PM
@xzsawq21 First of all, its always a good practice to post new queries in a separate thread as this thread resolved your original query. Helps your query get visibility along with helps other forum members who may have the same query.
Coming to your query, No, 7-series/Zynq LVDS buffers do not have internal biasing. you will need to use external biasing circuit for AC-coupled applications. Check Figure 1-72 from UG471