04-29-2020 06:13 AM
Hi Xilinx Team,
We are using Artix-7 XC7A200T-2FBG484I we saw there approx 40% less power consumption compared to commercial grade part.
Could you please tell us what is worst current requirement on VCCINT, VCCBRAM, VCCAUX
Total On Chip Power Dissipation we see 0.142W and what is maximum power dissipation ?
Thank you in advance
04-29-2020 06:31 AM
If you can share your observation and results will be much helpful.
I hope going through video provided at https://www.xilinx.com/video/hardware/power-estimation-analysis-using-vivado.html will be helpful for you.
Vector (SAIF) Based Power Estimation is most accurate way to get accurate results from power estimation. If you are planning to go for Vector (SAIF) Based Power Estimation, please refer to UG907 (v2019.2): Page 34~36, 37~44, chapter 5 and refer examples provided in UG997 (v2019.2) .
04-29-2020 08:35 AM
Artix-7 is not an ASIC... You cannot just obtain a max power parameter. In an FPGA power is heavily defined by the characteristics of your design that is put into it. Maximum power dissipation should be shown by XPE considering accurate information is entered into the estimation fields. Make sure to set process to Maximum.
04-30-2020 02:40 AM
Thank you for quick response
we took up XPE Calculator and could see power consumption of current (image XPE_2), we are in beginning stage of design with minimal details like max 15 LVDS input at 1.2GHz(max) and having max clock upto 1GHz(assumption) with other peripherals like SPI(150MHz) UART, I2C Interfaces.
we are deciding on power regulator for VCCINT, VCCBRAM,VCCAUX and would like to know maximum current on these power pins.
Bank 0,14,15 - 3.3V, Bank 13,34,35 - 1.8V, Bank 16 -2.5V
We are referring to Eva boards on better understanding of power consumption.
@bpatil Is there any way we can make this post to private mode ? or have local support.
Thanks in advance.
04-30-2020 03:19 AM
I think your assumptions are wrong. There is no way that you are going to get a 1GHz clock inside an Artix 7. On the -2 speed grade, the absolute limit for the clock routing is under 700MHz, and realistically it'll be extremely difficult to run the fabric over about 300MHz. I/O performance (the 1.2GHz LVDS you stated) are different because you can use the SERDES to translate between a wide, slow interface and a narrow, fast interface.
04-30-2020 09:39 AM - edited 04-30-2020 09:43 AM
Ok, if you don't know what design you can or cannot implement on the device why don't you first actually build a functional test design on the dev board if you have one? This will give you some idea of how much power you can expect for a particular sort of design weather it be a Ethernet, DDR3, PCIE, Video/DSP and so on. Doing this also will help realize the limitation of the device as Vivado will only let you configure the device within it's capability. I mean you could also read our documentations but it seems you've already skipped that portion. Otherwise how are you expecting to size your supply regulators if you don't know your design thus not knowing how much they'll demand of the supply rails? Not only will this solidify your design in regards to functionality as the scholar has mention above it will give you a more accurate and realistic reading of your power requirements...
05-01-2020 02:58 AM - edited 05-01-2020 03:00 AM
I agree with @tenzinc, FPGA power consumption varies with design. I will recommend you to go through "Seven Steps to an Accurate Worst-Case Power Estimation Using Xilinx Power Estimator" section provided in UG907 (v2019.2) : Chapter 2.
Please note XPE is for initial estimation power (power budgeting) and XPE accuracy is ± 20% (after correctly following all the guidelines provided Xilinx). XPE result are not as accurate as Vivado Report Power tool. This explained well in UG907 (v2019.2): Page 13~15.
As you are working on your regulator selection for VCCINT, VCCBRAM and VCCAUX (and also other power rails of FPGA); Vector (SAIF) Based Power Estimation is most accurate way to get accurate results for power estimation. If you are planning to go for Vector (SAIF) Based Power Estimation, please refer to UG907 (v2019.2): Page 34~36, 37~44, Chapter 5 and refer examples provided in UG997 (v2019.2)
Please note voltage rail regulator supply current should be more than estimated current draw (considering various parameter such as tolerance, PVT variation, power on current requirement..etc..)
You can take a look at our Evaluation Boards in case you need a starting point or simplify understanding.