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Adventurer
Adventurer
12,084 Views
Registered: ‎06-10-2014

Power estimation vs. measured temperature (Vivado 2014.1)

Hi,

 

Using Vivado 2014.1 with KC705, I made a small design with almost no logic and several GTXs (most used for PCIe). As the power estimation was modest,  I took the board's fan off. To be sure about it, I monitored the junction temperature, as reported by XADC, within Vivado's Hardware Manager.

 

The measured temperature settled at 60 degrees, even though the power report promised 43.4 degrees. I had set the environment conditions to a low profile heatsink + no airflow. As is evident from the snippet of Vivado's post-implementation power report below, Vivado adjusted TJA to 5.9 C/W accordingly.

 

The design worked perfectly, and the temperature remained within the operation range. I'm just worried about this mismatch between the estimation and what I actually got. So what could possibly be wrong?

 

Option 1: The power estimation is wrong. But why? 90% of the estimated power is accounted for GTXs and static power. Except for these GTXs, the I/O is just LEDs and push buttons. This leaves very little uncertainty on the toggling rate. It's not as if there was logic with unknown behavior here.

 

Option 2: The thermal resistance is wrong. So let's calculate it: With an ambient temperature of 25 degrees, we have a 35 degrees difference on 3.1W. That's 11.3 C/W, which is higher than any given theta for XC7K325T with an FFG900 package in ug475, table 5-1 (TJA alone is given as 9.7 C/W). 11.3 C/W is worse than with no heatsink at all, and no power dissipation towards the board. That little heatsink on KC705 is maybe not impressive, but it's surely better than nothing.

 

So -- can anyone shed some light on this? Is there any hidden power dissipation, not appearing in the report? Or what?

 

Thanks in advance,

  Eli

 

Excerpt from power report from Vivado 2014.1:

 

1. Summary
----------

+--------------------------+-------+
| Total On-Chip Power (W)  | 3.106 |
| Dynamic (W)              | 2.828 |
| Device Static (W)        | 0.278 |
| Total Off-Chip Power (W) | 0.000 |
| Effective TJA (C/W)      | 5.9   |
| Max Ambient (C)          | 66.6  |
| Junction Temperature (C) | 43.4  |
| Confidence Level         | Low   |
| Setting File             | ---   |
| Simulation Activity File | ---   |
| Design Nets Matched      | NA    |
+--------------------------+-------+


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.060 |       10 |       --- |             --- |
| Slice Logic              |     0.014 |    16593 |       --- |             --- |
|   LUT as Logic           |     0.012 |     6838 |    203800 |            3.35 |
|   Register               |     0.001 |     7552 |    407600 |            1.85 |
|   CARRY4                 |    <0.001 |      430 |     50950 |            0.84 |
|   F7/F8 Muxes            |    <0.001 |      112 |    203800 |            0.05 |
|   Others                 |     0.000 |      513 |       --- |             --- |
|   LUT as Distributed RAM |     0.000 |      372 |     64000 |            0.58 |
|   BUFR                   |     0.000 |        1 |       208 |            0.48 |
|   BUFG                   |     0.000 |        1 |        32 |            3.12 |
|   LUT as Shift Register  |     0.000 |        5 |     64000 |           <0.01 |
| Signals                  |     0.023 |    12978 |       --- |             --- |
| Block RAM                |     0.043 |      9.5 |       445 |            2.13 |
| MMCM                     |     0.108 |        1 |        10 |           10.00 |
| PCIE                     |     0.045 |        1 |         1 |          100.00 |
| I/O                      |     0.006 |       55 |       500 |           11.00 |
| GTX                      |     2.529 |        9 |        16 |           56.25 |
| Static Power             |     0.278 |          |           |                 |
| Total                    |     3.106 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.516 |       0.370 |      0.146 |
| Vccaux    |       1.800 |     0.092 |       0.060 |      0.032 |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |
| Vcco25    |       2.500 |     0.001 |       0.000 |      0.001 |
| Vcco18    |       1.800 |     0.001 |       0.000 |      0.001 |
| Vcco15    |       1.500 |     0.003 |       0.002 |      0.001 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.006 |       0.003 |      0.003 |
| MGTAVcc   |       1.000 |     1.237 |       1.219 |      0.018 |
| MGTAVtt   |       1.200 |     0.901 |       0.890 |      0.010 |
| MGTVccaux |       1.800 |     0.031 |       0.031 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is completely routed                            |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 5.9                      |
| Airflow (LFM)         | 0                        |
| Heat Sink             | low (Low Profile)        |
| ThetaSA (C/W)         | 3.3                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+

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15 Replies
Xilinx Employee
Xilinx Employee
12,070 Views
Registered: ‎08-01-2012

Did you do run simulations as per your application and generated .saif/.vcd files? That helps to estimate accurate dynamic power. 

________________________________________________

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Adventurer
Adventurer
12,064 Views
Registered: ‎06-10-2014

Hi,

 

No, there was no simulation data involved. But I can't see why that should matter, as the proportion of fabric logic is less than 10% of the estimated power consumption.

 

As for simulating the GTXs, the power tool should assume that the input data is random, which is was -- because the data is scrambled in any properly designed real-life application (or practically random by other means).

 

Thanks,

  Eli

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Scholar
Scholar
12,063 Views
Registered: ‎06-23-2013

I had similar problems with the XPE, though my problem surrounded LVDS I/O. I finally gave up on XPE and started using the IBIS and now FloTherm and IcePak files to estimate power and temperature.

 

I had to laugh at this answer from the moderator I received to my question why the calculated power was too low for LVDS: http://forums.xilinx.com/t5/Design-Tools-Others/Vivado-2013-3-power-calcs-for-LVDS-on-Kintex-7/m-p/387157

 

"In LVDS part of source power returns back."

It is more work to use the other models but I am getting a more accurate estimate this way.
Daniel

 

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Xilinx Employee
Xilinx Employee
12,044 Views
Registered: ‎01-03-2008

> So -- can anyone shed some light on this?

 

You should start by first measuring the power consumption on each of the power rails to see how it matches up against the power report.

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Teacher
Teacher
12,031 Views
Registered: ‎03-31-2012

are you able to measure the current on individual rails for KC705? that would tell you how accurate the power numbers are.
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Adventurer
Adventurer
12,018 Views
Registered: ‎06-10-2014

Hello,

 

Thanks for your answers. It seems like there's no obvious reason for my situation. So I'll get myself one of those usb-to-gpio adapters, and make some current readings. But that will take a couple of weeks (even though it's only $50). Formalities... We'll have to wait and see.

 

Regards,

  Eli

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Teacher
Teacher
12,016 Views
Registered: ‎03-31-2012

I am not sure why you need other than the board itself to measure the currents. The TI chips tell you the currents on most rails over I2C.
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Adventurer
Adventurer
12,009 Views
Registered: ‎06-10-2014

 Hi. 

Well, as far as I understand, the recommended way is to purchase an adapter and use a piece of software that is supplied by TI to do the current readings.

 

I'm aware that the PMBus wires go to the FPGA as well, but going that way requires a certain amount of design efforts. Besides, if I happen to send the wrong command as I develop this piece of logic, I'm not sure how healthy that will be to the board...

 

Thanks,

  Eli

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Xilinx Employee
Xilinx Employee
11,999 Views
Registered: ‎01-03-2008

There is no need to purchase the USB PMBUS adapter.  You can measure the voltage across the voltage sense resistors using a DVM and calculate the current from the resistance.

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Adventurer
Adventurer
7,568 Views
Registered: ‎06-10-2014

Hi,

 

It didn't cross my mind to measure the currents directly, I have to admit. Those sensing resistors are easy to find on the board, it turns out.

 

So I ran through a measurement of all 11 sensing resistors. The results are as follows (also attached as a pdf below):

 

currents.png

I had to take the card off the computer to do this, so the PCIe lanes were idle. The measured power consumption is slighly lower than before, and the temperature settled on 56 degrees this time.

 

The R voltage drops were measured between the V1 and V2 terminals (except for R170, which is a 2-terminal resistor). The supply voltages column contains measured voltages against ground (rounded off, but measured). The currents are calculated, of course, based upon R=0.005.

 

I'll save you the work of comparing with the power report, and get to the bottom line: All currents, except one, match the power report's estimation within the measurement error's tolerance.

 

The problem is with the 3.3V supply, which should have had zero current, and it draws ~0.42A. I double-checked this measurement, and also that the voltage to ground is indeed 3.3V. So I didn't probe the wrong resistor. The power report's estimation of zero current on this power rail is based upon a simple fact: Not a single I/O pad is defined with a 3.3V-related I/O standard. There are just eight LEDs, with LVCMOS15 and LVCMOS25.

 

Based upon the measured total power and the temperature, we have an effective Theta of (56-25)/4.25 = 7.3 C/W, which is a figure I can make sense of.

 

So the remaining question is: Why is there any current on the 3.3V rail?

 

Thanks,

   Eli

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Teacher
Teacher
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Registered: ‎03-31-2012

VCC3V3 (not VCC3C3, right?, no such net on the schematic) supplies a lot of other ICs on the board. It's not for the FPGA at all.

Also within the PC, it is possible that the ambient is higher than 25C.
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Adventurer
Adventurer
7,562 Views
Registered: ‎06-10-2014

Hi,

 

Yes, it's VCC3V3, and it's indeed powering some other devices (oscillators in particular). So 400 mA now makes sense.

 

The ambient temperature is 25 degrees. Even when attached to a PC, it's all in the open air.

 

So the power reports seems to be fine. The issue is probably purely thermal. Which isn't really a problem, as the whole story begins with dropping the fan, which isn't exactly following the instruction manual. ;)

 

Thanks,

   Eli

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Newbie
Newbie
550 Views
Registered: ‎11-17-2020

Hi guys,

after years from the first post ... I've just come across the same problem.

I'm encountering the problem with the Digilent "ARTY boards", either the one with the Artix-7 and the one with the Spartan-7. I wrote to Digilent and they told me they didn't characterize that board from this point of view. Also, they were aware about the temperature mismatch of about 4-6 degrees between the estimated and the measured ones.

In my case the problem is that the "estimated" FPGA temperature (using the Power Estimator tool, the XPE spreadsheet ... is "lower" and different from the "measured" one (using the onboard XADCs) of about 10 degrees, eventhough the bitstream of a very minimal and low consumption project was downloaded on it (one flipflop that toggles with the clock). It is important for me to get a better understanding of its thermal behavior.

Thank you for your help.

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Teacher
Teacher
540 Views
Registered: ‎07-09-2009

you are much better off starting a new thread,

But
the estimator is just that ,
think about the recent us elections, where the pollsters had oodles of accurate information, and did they predict it right.

The estimator works with a guess you give it , and an estimate of the average device parameters, on an average board cooling,

Its an estimate, the more you give it accurately the better,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Newbie
Newbie
441 Views
Registered: ‎11-17-2020

Hi drjohnsmith,

Thanks for your reply.

We eventually decided to give up using that temperature-estimation tools. You can't trust them. 

Thank you!