09-07-2018 08:23 AM
I will be very detail:
Part of my project requires the reading of uninitialized (power-up values) of BRAM in an Atrix-7 FPGA.
There are researches that exploited BRAM power gating and partial reconfiguration of Zynq 7020 FPGA. The procedure is pretty straightforward:
1. Load a partial bitstream with a BRAM instantiated and initialized. The static part has a UART module to send the data.
2. Load another partial bitstream that has no BRAM (I used some dummy logics with same I/O features as BRAM) [so it should disconnect the previous BRAMs from power gate]
3. Load third manipulated bitstream that has BRAM instantiation but no initialization. This time BRAM instantiated but initial values are deleted from FDRI block in the .rbt file [after 0x50xxxxxx command]. The header is adjusted accordingly. The FPGA gives me the value initialized at step 1! That means the FPGA is reading the RAM correctly but at step 2 it's not disconnecting the BRAM. In other words, power gating is not working.
Now the official documents say 7 series FPGAs are capable of power gating. That is uninstantiated blocks should be disconnected. But for my design, I do not see it. Also, since I deleted all the frames in the FDRI block [from partial bitstream], how the FPGA knows which RAM I am going to read? Is power gating not enabled by default in Artix-7? What am I missing here?
I would be happy to provide more information. Thanks for reading this long messages.
09-08-2018 07:00 AM
The BRAM is tested with 0, 1, checkerboard, checkerboard bar, then loaded from the bitstream before use. So, using BRAM for PUF is impossible.
09-08-2018 11:01 AM
Although the paper says we can, for the sake of argument I am assuming we cannot use BRAM for PUF application.
Then, I can see that the third step is not initializing the BRAM because it is reading values from previous steps. Why is the FPGA not turning off the BRAM in the step-2 even if the BRAM is not instantiated there? Why is it retaining values from a different bitstream?
09-08-2018 05:55 PM
There is a whole 'bram brain' that tests the bram, replaces any bad column (a bad bit) with a spare bit, and initializes the contents per the configuration.
Powering down this complex block, and powering it back on, is much much more than simply powering on and off a simpler ASIC dual port SRAM array.
09-08-2018 08:16 PM
I am kind of interested in this idea.
What you are saying is correct. However, UG473 , page 23 says uninstantiated blocks are turned off. So, if a partial bitstream does not have instantiation of BRAM, it should disconnect it from power network. So, BRAM should not have the values loaded previously (which is clearly not the case according to @jubayer`s post). That being said, BRAM is holding its previous value when the partial block is rewritten with a new kind of module that has only some logic, no BRAM. Why ? Note, he clearly mentions that he can read the BRAM values that was written in step-1 using a manipulated bitstream.