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Adventurer
Adventurer
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Registered: ‎08-22-2019

Powerup sequencing

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Hi. What is power up sequencing in 7 series FPGAs. And why do we need to follow powerup sequencing? If I am using artix7 xc7a35t FPGA what powerup sequencing do I need to include in my design? I have a custom(xc7a35t) board in which the engineer have used 4 channel LDO and i don't see there is power up sequencing and other hand I have a custom board(xc7k420t) in which I can see for powerup sequencing to produce delays they have used particular ICs between few voltages of this FPGA. Can anyone please explain in easiest way so that I can understand.. Thank you xilinx team. I have always got perfect informations here for whatever I have been seeking for.
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Re: Powerup sequencing

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Hi @mubasheerahmed_12 ,

What is power up sequencing in 7 series FPGAs. And why do we need to follow powerup sequencing? If I am using artix7 xc7a35t FPGA what powerup sequencing do I need to include in my design?

>> The recommended power-on sequence is to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.

For Artix 7, please refer page 8 of DS181 (v1.25), regarding Power sequencing.

Sequence in the data sheet is what is characterized, and tested.  Any sequence will work, except if specifically prohibited in the data sheet.

Current may be slightly more than specified for the sequence shown, and IO may not be tristate while powering ON in a different sequence (you should check if this is important in your design, and most sequences will still have correct tristate IO behavior -- you would need to verify for your sequence).

Hope this helps.

Regards,
Deepak D N
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Re: Powerup sequencing

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Hi @mubasheerahmed_12 ,

What is power up sequencing in 7 series FPGAs. And why do we need to follow powerup sequencing? If I am using artix7 xc7a35t FPGA what powerup sequencing do I need to include in my design?

>> The recommended power-on sequence is to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.

For Artix 7, please refer page 8 of DS181 (v1.25), regarding Power sequencing.

Sequence in the data sheet is what is characterized, and tested.  Any sequence will work, except if specifically prohibited in the data sheet.

Current may be slightly more than specified for the sequence shown, and IO may not be tristate while powering ON in a different sequence (you should check if this is important in your design, and most sequences will still have correct tristate IO behavior -- you would need to verify for your sequence).

Hope this helps.

Regards,
Deepak D N
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