09-29-2018 08:10 AM
I am using spartan 6_XC6SLX9.
In "Spartan-6 FPGA Clocking Resources" doc [UG382] , in page 68, table 2-4 , there is a equation for "Maximum Number of DCM Delay Steps" . In this equation there is a term "INTEGER" and i did't find it's value.I searched in this doc and in "DC and Switching Characteristics" doc [DS162] but i did,i find any thing.
Can anyone explain it ??
How can i find it ??
09-29-2018 10:03 AM
INTEGER only means to truncate the number to the nearest lower integer value. (i. e. drop the fractional part after the calculation).
09-30-2018 01:31 AM
I did't understand what you mean ... sorry ... can you explain more about this please ??
Thank you for your reply.
09-30-2018 07:48 AM
Perhaps I can help,
The DCM has a delay line with taps every 35ps. The delay line is long enough to contain one clock cycle at the minimum frequency specified (~ 20 MHz, or 50ns). So, if the clock is a much higher frequency (say 500 MHz), the period in the delay line is 2ns worth of taps ~57 (the remainder are not used).
So, a step in phase cannot be smaller than 35ps, and the control can only step from >0 degrees, to 360 degrees, regardless of clock frequency.