09-26-2014 08:22 AM
Anyone else trying to simulate programming the MMCM via the DRP? I seem to be encountering some undocumented features of the DRP and/or MMCM.
As soon as I try to do a fractional divide on CLKFBOUT ("M" on the block diagram in XAPP888) I have to subtract 2 from the integer part of the divide value, as though setting the FRAC bits to 1, for example gives a divide value of 2.125 rather than the expected 0.125. And this is only if the integer part of the divide value is an even number. When the integer part is odd the ouput frequency jumps up even farther, as though the FRAC bits are adding even more to the divide value. So far I haven't been able to determine exactly what integer value it's adding.
Anybody else having problems like this? Is this a problem with the simulation model or does the real MMCM behave this way also? Any help would be much appreciated.
09-26-2014 09:54 AM
There is a direct XAPP on DRP using MMCM. http://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf.
There is a design with this xapp, which you can simulate. You can modify the values, as suggested in the xapp to make necessary changes.
09-26-2014 10:21 AM
Thanks. But as I stated, I am working from XAPP888. I have also simulated the reference design. True, I have not tried to modify the reference design to generate other frequencies, but I am basically running the DRP the same as the reference design: reading, masking, and writing the registers in the same order; only with my own design.
I have been unable to generate 786 MHz from a 16 MHz input, for example; although it clearly should work according to the parameters of XAPP888. This is only one example. It seems that anytime "M" has an odd integer value, the fractional part will not work as expected or described in XAPP888. But, I am happy to be proved wrong.....
02-03-2015 03:57 PM
I was having the same problem with DRP.
I'm not sure what dwieberd's solution was, but looking at the simulation of the XAPP888, it appears that for fractional divides, the high and low time both need to be 1 less than normal, and for odd values, the high time should be one more than low time (whereas for normal odd values, low time should be 1 more than high time).
When I simulated the code from the XAPP888, the simulation said the frequency for fractional divides was off. However, when I ran my code on an actual FPGA (with the values from the simulation), the output frequency was correct.
For example, while simulating the reference design, I had an input clock of 27 MHz, set M to 34 MHz, D to 1, and the clkout divide to 13.125. Looking at the simulation waveform, the high time was set to 6 and the low time was set to 5, and the simulation showed the output to be 80 MHz (which is what you expect if fractional divides work like normal divides). However, when I set a real FPGA with a high and low time of 6, 5 I get an output of 70 MHz.
But, when simulating with a clkout divide of 14.125, the simulation shows a correct output of 65 MHz (which a high time of 6 and a low time of 6). The FPGA also outputs 65 MHz.
So there seems to be a problem with the documentation and simulation of the DRP. The documentation doesn't mention anything about changing how high/low time works with fractional divides, and simulating the reference design (at least when I simulated it) showed an incorrect output frequency.
02-15-2017 02:29 PM - edited 02-15-2017 03:04 PM
Hi Xilinx Team,
Even i am stuck with "NOT MUCH helping" documentation.
1. can you point me to latest code of mmcm_drp.v and mmcm_drp_func.h for artix 7 and ultrascale devices
[though, i am referring this code https://github.com/warclab/prcontrol/blob/master/mmcm_drp.v
i believe the the code is too old]
2. Filter and Lock LUTs are different for each device family [Artyx, Virtex, Ultrascale]?
3. Do you have an .xls to compute MMCM register values based on
divide - 8 bits
phase - 32 bits
duty cycle - 32 bits
02-15-2017 03:32 PM
You can download the latest version of the appnote xapp888 here:
Towards the bottom of the document is a link that point you to the latest version of the code for 7-series and Ultrascale.
Yes, every silicon generation (e.g. all 7-series vs all Ultrascale vs all UltrascalePlus usually have some differences. You can see that in the datasheets.
02-25-2019 06:25 PM
I have the same problem,when the divider is fractional,the result is wrong,but in the actual FPGA,the result is right（download bit file to KC705）。Do you solve this prolem?How solve?
02-25-2019 06:37 PM
I have a problem of MMCM_DRP,In simulation,when the divider of clkout0 and the multiplier of clkfbout are fractional,the result is wrong（clkout0 is not the frequency as I respected）.but in actual FPGA,the result is right。How to resolve the problem。
03-18-2020 01:22 PM
MMCME3_ADV and modified XAP888 mmcme3_drp.v and top_mmcme3.v.
I was getting incorrect CLKOUT frequencies in simulation for some fractional divider ratios until I realized the CLKOUT fractional parameters in CLKOUT ClkReg2 were not being updated.
The CLKOUT frequencies in simulation for fractional divider ratios are correct when the CLKOUT fractional parameters in CLKOUT ClkReg2 are updated.