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Explorer
Explorer
254 Views
Registered: ‎07-10-2008

Question about Xapp1017 bitslip

We have used the example in Xapp1017 as reference to convert LVDS serial data to parallel data .

currently, we have a question regarding to bitslip module; in UG471_7Series_SelectIO, it is mentioned bitslip is sync triggered by clock CLKDIV.

1.png

In our program as attached figure, PIX_clk is the CLKDIV, SYNC_OUT is the output parallel data, but when bitslip is HIGH and PIX_clk is toggled, SYNC_OUT is not changed. Please let us know, how can we shift data to the correct position?

Many thanks.

David.

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Community Manager
Community Manager
161 Views
Registered: ‎08-08-2007

Re: Question about Xapp1017 bitslip

Hi @hg81 

 

Can include the input to the ISERDES in the picture. There is a latency associated with the ISERDES so it does take some CLKDIV cycles to pass through. If we can see the input as well that can help us trace through. 

Sandy

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