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Observer
Observer
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Registered: ‎07-27-2018

Question about various clock trees.

Hi. all

I wonder what each means for the Clock Tree, which is written in part  "Clock Buffers and Networks" of the DS162(Spartan-6 DC and Switching Characteristic).

Various lock trees => Global clock tree, I/O clock tree, BUFPLL clock tree

 

and  "Set/Reset" of Part "CLB Switching Characteristics(SLICEM Only)" of DS165

What is the Toggle frequency??

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Adventurer
Adventurer
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Registered: ‎06-05-2015

Dear tvgod,

the timings mentioned are for the different clock networks. Consider reading ug382, if u want a detailed explanation for the different buffer types.

 

The BUFG is the global clock buffer and it reaches every FF and design element in the FPGA, including IO, DSP, BRAM, FFs.

The BUFIO is an IO Clock Buffer, which reaches IO Elements like ISERDES, OSERDES, IDDR and ODDR or simple IOB Registers. It cannot drive FPGA logic.

The BUFPLL is a PLL related buffer that can only be used to connect the PLL with IO components.

 

Not sure what the toggle frequency means in this context, but Set/Reset refers to the timing related to the Set-Input of a FF and the Reset-Input of an FF. I would assume that toggle frequency here means the maximum frequency at which u could toggle the Set/Reset Pin of a FF.

 

Best regards,

Martin