the timings mentioned are for the different clock networks. Consider reading ug382, if u want a detailed explanation for the different buffer types.
The BUFG is the global clock buffer and it reaches every FF and design element in the FPGA, including IO, DSP, BRAM, FFs.
The BUFIO is an IO Clock Buffer, which reaches IO Elements like ISERDES, OSERDES, IDDR and ODDR or simple IOB Registers. It cannot drive FPGA logic.
The BUFPLL is a PLL related buffer that can only be used to connect the PLL with IO components.
Not sure what the toggle frequency means in this context, but Set/Reset refers to the timing related to the Set-Input of a FF and the Reset-Input of an FF. I would assume that toggle frequency here means the maximum frequency at which u could toggle the Set/Reset Pin of a FF.