12-08-2015 06:31 PM - edited 12-08-2015 06:32 PM
Sadly, there are some weird gaps in the coregen IP these days, and they seem to get less flexible over time rather than more flexible. For instance, you (technically) can't create a MIG that can run from a 48 MHz USB clock anymore because they've severely restricted the clocking options. :( A rant from another thread...
What ADC part are you working with?
12-10-2015 05:19 AM
I am using AD9228 from Analog Devices. I am running it at 32MHz sampling clock.
I was stupid enough to install Vivado 2015.4 to see if anything had changed to better from 2015.2 and I just got a clock wizard change from vhdl/verilog to verilog only output. Not a big issue as I keep old Vivado releases for this kind of upsets, but it adds to the degenerating flexibility of Vivado.
12-11-2015 01:26 AM
I'm using AD9637 from Analog Devices.
We run it stable at 50Msps, and are close to achieve stable operation at 75Msps.
08-09-2016 09:40 PM
I'm using a ADS5281 it's a 12-bit ADC and I'm running it at 40Msps. I have two master SDR ISERDES, one running with data_p and one with data_n with data_p clocking in the even bits and data_n clocking in the odd bits. The odd bit ISERDES has an inverted bit clock and and I have DYN_CLKDIV_INV_EN and DYN_CLK_INV_EN set to true, but I still have not gotten anything out when I try and run it with hardware. It does not make sense to me to invert the divclk, but I have tried pretty much every combination of DYN_CLKDIV_ EN and DYN_CLK_INV_EN with clocks inverted and noninverted with no results. Do you have both ISERDES blocks with DYN_CLKDIV_EN and DYN_CLK_INV_EN set to true, and do you still invert the CLK in one?
08-10-2016 10:33 AM
I found the problem. I was using the lclk from my ADC for both of the ISERDES blocks. This worked in simulation, but did not work on hardware.
06-17-2019 07:22 AM
Hi, I'm trying to do the saming thing as you. I read the discussion of this thread about XAPP524. It's out of data. Could you please share your design about 12bit lvds ADC with DDR mode? Thank you very much.
06-17-2019 07:28 AM
The frequency of the DDR data stream must be such that it lies within the adjustment possibilities of the IDELAY element