09-12-2019 01:54 AM
I do not simulate
I want to lick both the rising and failing edge of the 1 entry How can I do this I'd try
if Signal_in'event and Signal_in='1' then
i <= i + 1;
elsif Signal_in2'event and Signal_in2='0' then
i <= i + 1;
if Signal_in'event then if Signal_in = '1' and edge_state=false then i <= i + 1;
edge_state <= true; elsif Signal_in = '0' and edge_state=true then i <= i + 1;
edge_state <= false;
09-12-2019 04:10 AM
First, "not works" is a poor description of your problem. Do you get an error message? Is it a syntax check error, a synthesis error or an Implementation error? What is the error message and what line in your code does it reference?
The only registers in a Xilinx FPGA that can respond to both the rising edge and falling edge of a clock are in the Input/Output tiles. Registers inside the FPGA can only respond to one edge of a clock.
Your code has multiple registers driving the signal "i". Only one register output may drive a signal.
Are Signal_in and Signal_in2 really clocks (constantly running periodic signals) or are they something else? Using a regular signal as the clock input to a register is very bad design practice.
09-12-2019 04:18 AM
A few other comments
welcome to the world of VHDL.
You will love and hate the strict constraints, stick with it its worth it.
a) Dont use Signal_in'event and Signal_in='1' , use if rising_edge( signal_in )
b) make certin this is inside a process with the correct sensetiity list
c) Always simulate... Simulatoin is quicker than synthesis and tells you a lot more about your circuit . You will spend may be 60 % of your life simulating, 30 % designing, and 10 percent waiting for synthesis.
d) always rember that your code is describing hardware, if you can't think what the hardware is , the its likely the tools can not either.
( and yes there are no DDR flip flops in the FPGA )
Why do yo u want DDR internal flipflops ?
09-12-2019 05:16 AM
if Signal_in'event and Signal_in='1' then i <= i + 1; elsif Signal_in2'event and Signal_in2='0' then i <= i + 1; end if;
Not possible to do within the FPGA.
Pay attention to what others have said above.