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Adventurer
Adventurer
1,049 Views
Registered: ‎11-17-2017

Select IO Interface Wizard can't instantiate ODELAY

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I'm using xc7z045ffg900-2.I want to connect FPGA and DA together, so I need to use ODELAY to meet the timing.But when I use the SelectIO Interface Wizard ,the ODELAY can't be instantiated.The IP seetings is:

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Moderator
Moderator
1,197 Views
Registered: ‎08-08-2017

Hi @chenyang1994

 

I have checked it in VIVADO 2018.1 at our end. Initially i have selected Xc7z045ffg900-2 as mentioned, ODELAYE2 primitive is not getting instantiated as you reported. I have also checked for other part i.e xc7k70tfbg484-3  and it is found that ODELAYE2 primitive is instantiated as expected. I will discuss this with development team and update you shortly.

 -----------------------------------------------------------------------------------------------------------------

Please reply if you have any queries, Give Kudos and accept as solution

------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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Adventurer
Adventurer
1,043 Views
Registered: ‎11-17-2017

The IP verilog file is:

 

`timescale 1ps/1ps

module selectio_wiz_0_selectio_wiz
// width of the data for the system
#(parameter SYS_W = 16,
// width of the data for the device
parameter DEV_W = 32)
(
// From the device out to the system
input [DEV_W-1:0] data_out_from_device,
output [SYS_W-1:0] data_out_to_pins_p,
output [SYS_W-1:0] data_out_to_pins_n,

output delay_locked, // Locked signal from IDELAYCTRL
input ref_clock, // Reference clock for IDELAYCTRL. Has to come from BUFG.
input clk_in, // Fast clock input from PLL/MMCM
input io_reset);
wire clock_enable = 1'b1;
// Signal declarations
////------------------------------
// Before the buffer
wire [SYS_W-1:0] data_out_to_pins_int;
// Between the delay and serdes
wire [SYS_W-1:0] data_out_to_pins_predelay;
wire ref_clock_bufg;
// Create the clock logic


assign clk_in_int_buf = clk_in; // clock coming from MMCM

// We have multiple bits- step over every bit, instantiating the required elements
genvar pin_count;
generate for (pin_count = 0; pin_count < SYS_W; pin_count = pin_count + 1) begin: pins
// Instantiate the buffers
////------------------------------
// Instantiate a buffer for every bit of the data bus
OBUFDS
#(.IOSTANDARD ("LVDS"))
obufds_inst
(.O (data_out_to_pins_p [pin_count]),
.OB (data_out_to_pins_n [pin_count]),
.I (data_out_to_pins_int[pin_count]));

// Instantiate the delay primitive
////-------------------------------


assign data_out_to_pins_int[pin_count] = data_out_to_pins_predelay[pin_count];

// Connect the delayed data to the fabric
////--------------------------------------
// DDR register instantation
ODDR
#(.DDR_CLK_EDGE ("SAME_EDGE"), //"OPPOSITE_EDGE" "SAME_EDGE"
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_inst
(.D1 (data_out_from_device[pin_count]),
.D2 (data_out_from_device[SYS_W + pin_count]),
.C (clk_in_int_buf),
.CE (clock_enable),
.Q (data_out_to_pins_predelay[pin_count]),
.R (io_reset),
.S (1'b0));
end
endgenerate

// IDELAYCTRL is needed for calibration
(* IODELAY_GROUP = "selectio_wiz_0_group" *)
IDELAYCTRL
delayctrl (
.RDY (delay_locked),
.REFCLK (ref_clock_bufg),
.RST (io_reset));

BUFG
ref_clk_bufg (
.I (ref_clock),
.O (ref_clock_bufg));
endmodule

 

 

So the IP doesn't instantiate the ODELAY. Why?

Thanks.

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Highlighted
Moderator
Moderator
1,198 Views
Registered: ‎08-08-2017

Hi @chenyang1994

 

I have checked it in VIVADO 2018.1 at our end. Initially i have selected Xc7z045ffg900-2 as mentioned, ODELAYE2 primitive is not getting instantiated as you reported. I have also checked for other part i.e xc7k70tfbg484-3  and it is found that ODELAYE2 primitive is instantiated as expected. I will discuss this with development team and update you shortly.

 -----------------------------------------------------------------------------------------------------------------

Please reply if you have any queries, Give Kudos and accept as solution

------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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Adventurer
Adventurer
987 Views
Registered: ‎11-17-2017

Thank you very much.

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Visitor
Visitor
365 Views
Registered: ‎04-18-2019

Hi pthakare,

It seems SelectIO Interface Wizard's ODLEAYE2 instatiation cannot be generated on all Zynq-7000 parts (I use xc7z045fbg676-2 and config to "Variable loadable"), but no problem for Kintex-7000 family. Any root cause updated form Xilinx development team? 

As for Zynq-7000 parts, is this only a behavior model simulation issue? or final IP generation on FPGA is going to be affected too?  

BRs,
Yi 

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