06-25-2019 11:48 AM
I've got a requirement to run a processor as slow as possible (EMI Reasons) and have been given a Zynq 7020 as a target chip.
What is the slowest clk speed I can clock this PS system?
I've sucessfully run the Microblaze softcore at 1MHz for experimental purposes but have yet to try the ARM cores.
From the Zynq datasheet the clock into the PLL has the following requirements:
FPSCLK PS_CLK frequency MIN: 30MHz MAX:60MHz
And the output clock is:
FPSPLL_MIN PLL minimum output frequency 780 MHZ
Does this mean that the slowest input clock we are able to use is 30MHz, and the slowest ARM core clock is 780MHz?
06-26-2019 04:09 AM - edited 06-26-2019 04:49 AM
There are dividers after the PLL to drive the various parts of the chip. The max CPU divider is 30, so you can get it down to 780/30 = 26MHz. You will have to put in at least 30MHz on the PS_CLK. You might also find that lower frequency doesn't necessarily mean better in terms of EMI, it depends more on edge sharpness than frequency, and you might find that running fast and being in sleep mode 95% of the time is better than running slowly.
06-26-2019 04:35 AM
The Zynq documentation should tell you the lowest clk freq.
@patstew is correct. Practically you can supply the PS with the lowest clock your MMCM/PLL can generate.
06-26-2019 05:17 AM
06-26-2019 05:22 AM
@dpaul24Thank you for the reply, I was only able to find the maximum frequency in the documentation unfortuantly, which is why I asked on here.
Ah....some Xilinx docs!
Find out the ARM core used and search directly ARM documentation for that. I would do so.
06-26-2019 05:25 AM
I very much doubt you'll find it, ARM can't know that kind of information, it depends on the specific chip implementation not the IP that ARM sell to Xilinx.