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Visitor hagaya
Visitor
288 Views
Registered: ‎12-10-2018

Soft Error Mitigation IP power considiration

Hi,

I want to implement the SEM IP on Artix 7. 

Is this IP a pure logic that i can consider it in my Power estimation or it is connected to sillicon technology and has a wide poer effect

Hagay

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Xilinx Employee
Xilinx Employee
258 Views
Registered: ‎06-06-2018

Re: Soft Error Mitigation IP power considiration

Hi @hagaya,

 

SEM Controller Resource ultilization derived from post synthesis for Artix 7 devices are given in Page 27 of PG036.

You can estimate the power by using Xilinx Power estimator by following this UG440 (v2013.3/14.7).

If you have the design, you can use Vivado power for more better results by following UG907.

Regards,

Deepak D N

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