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Explorer
Explorer
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Registered: ‎07-03-2014

[Spartan6] Two IO pins shortcircuited... Could be this a problem?

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Hi everyone!

Due to a manufacturing problem, two pins in my Spartan6 custom board are connected, but they shouldn't be that way: pin N24 is a clock output in bank 1, which is powered at 3.3V, and it is connected to M24 (which is adjacent to N24) in an inner layer of the PCB; pin M24 belongs to bank 5 which is powered at 1.8V, but luckly that pin is not used in my FPGA design.

Could there be any problem because of this connection? The 3.3V clock outputs pin N24 and it comes back to the FPGA through N24, which has VCCIO = 1.8V. DS162 (Spartan-6 FPGA Data Sheet: DC and Switching Characteristics) states that maximum rating for any IO pin is 4.1V, regardless VCCIO, so it seems this manufacturing error won't render my board useless.

Must I set any special configuration in pin M24? I plan to set this pin as output and put it in High-Z to avoid voltage collision.

Am I right? Any suggestion?

Thanks in advance!

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Registered: ‎09-17-2018

The diodes are the body to substrate,

Always there, not selectable or programmable.  That is what I meant by intrinsic.

In earlier days, for PCI, some devices had extra transistors to isolate the body of the CMOS output stack devices, but I cannot recall if S6 had this or not.  So, back to these forums, and Viola!

https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/Spartan6-Which-IO-modes-have-clamp-diodes/td-p/124928

Seems to imply you have them off, unless you set it to PCI.

Try it, look at the voltage.  If it does not clamp, woo-hoo!

lowearthorbit

(Way too much has transpired to be able to remember all these details...and I doubt anyone is still there at Xilinx who knows any of this any longer)

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6 Replies
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Registered: ‎09-17-2018

Yes,

The 3.3v driver will get clamped by the 1.8v bank IO pin intrinsic diodes (always there as they are inherent in the CMOS IO transistors).  The diode to Vcco = 1.8v will get forward biased, driving the 1.8v up to ~ 3.3 - 0.7 = 2.6v which will destroy destroy the 1.8V IO devices. (Beyond the Abs Max in Table 1).

lowearthorbit

 

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Registered: ‎09-17-2018

Oops,

Spartan 6 is OK (Table 1), Spartan 7 is not.  Ugly, but the clamp to ~ 2.6v shouldn't hurt it.

lowearthorbit

Explorer
Explorer
497 Views
Registered: ‎07-03-2014

Thanks for your answer, @lowearthorbit!

What if I set pin M24 to open-drain? Clamping diodes will be put in forward too? Isn't there any way to get a clean clock ouput from N24 in this weird situation?

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Registered: ‎09-17-2018

The diodes are the body to substrate,

Always there, not selectable or programmable.  That is what I meant by intrinsic.

In earlier days, for PCI, some devices had extra transistors to isolate the body of the CMOS output stack devices, but I cannot recall if S6 had this or not.  So, back to these forums, and Viola!

https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/Spartan6-Which-IO-modes-have-clamp-diodes/td-p/124928

Seems to imply you have them off, unless you set it to PCI.

Try it, look at the voltage.  If it does not clamp, woo-hoo!

lowearthorbit

(Way too much has transpired to be able to remember all these details...and I doubt anyone is still there at Xilinx who knows any of this any longer)

View solution in original post

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Explorer
Explorer
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Registered: ‎07-03-2014

Thanks for all that information, @lowearthorbit!

I finally decided to set M24 pin as an input (instead of a High-Z output) and I will rely on absolute maxim Vin of 3.95V and that no clamping diodes are present.

The boards will arrive next week from factory, I'll check if everything is ok by then.

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Explorer
Explorer
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Registered: ‎07-03-2014

The boards finally arrived and checked if they worked, and they did! I set M24 (the undesired shotcircuited pin) as an LVCMOS33 input (even thought it is in a 3.3V bank, but ISE 14.7 didn't complain) and I have got a perfectly clean 3.3V clock output from N24.

Thanks godness that Spartan 6 hasn't got any clamping diode in the input IOBs...

Thanks for the support!

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