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Adventurer
Adventurer
414 Views
Registered: ‎12-16-2010

Spartan6 with DDR3 IOB conflict

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Hello,

we successfully employed the MIG with a DDR2 memory connected on bank1.

Now I'm trying to upgrade to DDR3, so I changed the UCF file according to newer I/O standard requested (I simply copied relevant data from the UCF generated by core_generator).

NET  "dram_reset_n_out"       IOSTANDARD = SSTL15_II;
NET  "dram_ck_out"            IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_ck_n_out"          IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_cke_out"           IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_a_out[*]"          IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_ba_out[*]"         IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_ras_n_out"         IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_cas_n_out"         IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_we_n_out"          IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_odt_out"           IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_dq_inout[*]"       IOSTANDARD = SSTL15_II | IN_TERM = NONE | OUT_TERM = UNTUNED_50;
NET  "dram_dm_out"            IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_udm_out"           IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_dqs_inout"         IOSTANDARD = DIFF_SSTL15_II | IN_TERM = NONE | OUT_TERM = UNTUNED_50;
NET  "dram_dqs_n_inout"       IOSTANDARD = DIFF_SSTL15_II | IN_TERM = NONE | OUT_TERM = UNTUNED_50;
NET  "dram_udqs_inout"        IOSTANDARD = DIFF_SSTL15_II | IN_TERM = NONE | OUT_TERM = UNTUNED_50;
NET  "dram_udqs_n_inout"      IOSTANDARD = DIFF_SSTL15_II | IN_TERM = NONE | OUT_TERM = UNTUNED_50;
NET  "dram_rzq_inout"         IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET  "dram_zio_inout"         IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;

 

While it worked as expected with DDR2 and VCCO=1.8, now ISE gives an error I don't understand:

ERROR:Place:864 - Incompatible IOB's are locked to the same bank 1
   Conflicting IO Standards are:
   IO Standard 1: Name = SSTL15_II, VREF = 0.75, VCCO = 1.50, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = NR
   List of locked IOB's:
       DRAM_zio_inout
       DRAM_rzq_inout
       DRAM_dq_inout<0>
       DRAM_dq_inout<1>
       DRAM_dq_inout<2>
       DRAM_dq_inout<3>
       DRAM_dq_inout<4>
       DRAM_dq_inout<5>
       DRAM_dq_inout<6>
       DRAM_dq_inout<7>
       DRAM_dq_inout<8>
       DRAM_dq_inout<9>
       DRAM_dq_inout<10>
       DRAM_dq_inout<11>
       DRAM_dq_inout<12>
       DRAM_dq_inout<13>
       DRAM_dq_inout<14>
       DRAM_dq_inout<15>
ERROR:Place:864 - Incompatible IOB's are locked to the same bank 1
   Conflicting IO Standards are:
   IO Standard 1: Name = SSTL15_II, VREF = NR, VCCO = 1.50, TERM = NONE, DIR =
   OUTPUT, DRIVE_STR = NR
   List of locked IOB's:
       DRAM_reset_n_out
ERROR:Place:864 - Incompatible IOB's are locked to the same bank 1
   Conflicting IO Standards are:
   IO Standard 1: Name = SSTL15_II, VREF = NR, VCCO = 1.50, TERM = NONE, DIR =
   OUTPUT, DRIVE_STR = NR
   List of locked IOB's:
       DRAM_dm_out
       DRAM_cke_out
       DRAM_a_out<0>
       DRAM_a_out<1>
       DRAM_a_out<2>
       DRAM_a_out<3>
       DRAM_a_out<4>
       DRAM_a_out<5>
       DRAM_a_out<6>
       DRAM_a_out<7>
       DRAM_a_out<8>
       DRAM_a_out<9>
       DRAM_odt_out
       DRAM_udm_out
       DRAM_ba_out<0>
       DRAM_ba_out<1>
       DRAM_ba_out<2>
       DRAM_a_out<10>
       DRAM_a_out<11>
       DRAM_a_out<12>
       DRAM_cas_n_out
       DRAM_we_n_out
       DRAM_ras_n_out
ERROR:Place:864 - Incompatible IOB's are locked to the same bank 1
   Conflicting IO Standards are:
   IO Standard 1: Name = DIFF_SSTL15_II, VREF = NR, VCCO = 1.50, TERM = NONE,
   DIR = OUTPUT, DRIVE_STR = NR
   List of locked IOB's:
       DRAM_ck_out
       DRAM_ck_n_out
ERROR:Place:864 - Incompatible IOB's are locked to the same bank 1
   Conflicting IO Standards are:
   IO Standard 1: Name = DIFF_SSTL15_II, VREF = NR, VCCO = 1.50, TERM = NONE,
   DIR = BIDIR, DRIVE_STR = NR
   List of locked IOB's:
       DRAM_dqs_n_inout
       DRAM_udqs_n_inout
       DRAM_dqs_inout
       DRAM_udqs_inout

 

The IOBs are all using VCCO=1.5, so why they are conflicting?

Furthermore, I would add some LVCMOS15 on the same bank, but these also would be added to the conflicting list...

What is wrong?

 

Thanks

Andrea

 

 

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Adventurer
Adventurer
358 Views
Registered: ‎12-16-2010

Re: Spartan6 with DDR3 IOB conflict

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Hello,

I found the problem eventually.

I had added some inout signals expected to work with LVCMOS33. Enabling input termination obviously caused incompatibility with VCCO=1.5V, but the tool didn't notified this problem, so I was looking the cause in the wrong direction.

Thanks

Andrea

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3 Replies
Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎06-30-2010

Re: Spartan6 with DDR3 IOB conflict

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you need to regenerate the IP for DDR3 you cant simple change the UCF here, if you regenerate the IP targeting DDR3 does that show the same behaviour?

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Adventurer
Adventurer
359 Views
Registered: ‎12-16-2010

Re: Spartan6 with DDR3 IOB conflict

Jump to solution

Hello,

I found the problem eventually.

I had added some inout signals expected to work with LVCMOS33. Enabling input termination obviously caused incompatibility with VCCO=1.5V, but the tool didn't notified this problem, so I was looking the cause in the wrong direction.

Thanks

Andrea

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Xilinx Employee
Xilinx Employee
355 Views
Registered: ‎06-30-2010

Re: Spartan6 with DDR3 IOB conflict

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excellent great to hear you have resolved it

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