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1,653 Views
Registered: ‎03-03-2017

Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

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Hi, I am working on optimizing clocking on a design and I have run into a snag.   I need to have two possible clocks for a portion of the design so I have tried to implement a BUFGCRTL, but after doing that I seemed to have run into a problem.   I get the error/warning shown below (I put in CLOCK_DEDICATED_ROUTE FALSE into my XDC in order to let it implement).   With the CLOCK_DEDICATED_ROUTE FALSE in the XDC it implements but timing fails miserably.

Can somebody please help me debug this?

 

Warning: 

[DRC PLCK-1] Clock Placer Checks: Sub-optimal placement for a BUFG-BUFG cascade pair.
Resolution: A dedicated routing path between the two BUFGs can be used if they are placed in cyclically adjacent BUFG sites and both are in the same half (TOP/BOTTOM) side of an SLR. If this condition cannot be met, it is recommended that a BUFH be connected in series between the two BUFGs to ensure that clock region partitioning will account for the use of a clock spine for this connection.
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.

BUFG_LT_MFP0_DCARD_inst (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
LT_MFP0_DCARD_BUFGMUX_inst (BUFGCTRL.I1) is provisionally placed by clockplacer on BUFGCTRL_X0Y3

 

Schematic of circuit in question:

foo.png

 

Thanks.

Tim

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2,560 Views
Registered: ‎09-15-2016

Re: Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

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Hi @tim_severance

 

This error occurs due to placement of cascaded BUFGs in non-adjacent locations. To resolve this error you can write the constraints to lock the cascaded BUFG to adjacent locations in the same half of the device. Also as mentioned in the error resolution itself that you can put BUFH is series between two cascaded BUFG.

 

Regards

Rohit

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Regards
Rohit
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1,652 Views
Registered: ‎03-03-2017

Re: Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

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By the way I forgot to mention that I am using Vivado 2017.2 and this is an Artix-7 device with the following layout:

 

foo1.png

 

Tim

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2,561 Views
Registered: ‎09-15-2016

Re: Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

Jump to solution

Hi @tim_severance

 

This error occurs due to placement of cascaded BUFGs in non-adjacent locations. To resolve this error you can write the constraints to lock the cascaded BUFG to adjacent locations in the same half of the device. Also as mentioned in the error resolution itself that you can put BUFH is series between two cascaded BUFG.

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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1,615 Views
Registered: ‎04-18-2011

Re: Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

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Hi Tim
I am wondering why the bufg needs to be cascaded into the bufgctrl
How come you do it this way?
Why can't the pll drive the bufgctrl directly? It looks like the output of the first pll goes elsewhere. If you need to have a free running clock for one part of the design and also need to mux this with the external clock I see in the picture why not just add an extra output from the ppl?
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Registered: ‎04-18-2011

Re: Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

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Also cascaded bufg is not ideal in terms of jitter
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Registered: ‎03-03-2017

Re: Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

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Hi @klumsde,

   That is a good idea to use another MMCM output for this purpose.   I might go ahead and do that.

   I was able to add in the BUFHs and got implementation to pass, but now I am getting timing failures.

   Do you know what type of constraints I use to handle multiple clocks, as is shown below?

 

foo3.png

 

Thanks.

Tim

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Registered: ‎04-18-2011

Re: Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

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Make a Top level create clock port that drives the input to the mmcm, this will propagate to all outputs of the mmcm.
You will see generated clocks for all mmcm outputs if you do report_clocks
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