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Visitor
Visitor
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Registered: ‎10-07-2015

Suddnely high current on Vccint on Artix-7 (XQ7A200T-FFG1156)

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Hi everyone,

we have a problem using an Artix-7 FPGA. We developed a board carrying this FPGA, and in the end everything worked fine. But already two times, on two different boards, it happened that the current on the Vccint suddenly increased strongly, we estimate between 3 and 6 Amps. Of course, the FPGAs got very hot in this case. We changed the device and even with a mutimeter we can measure a short-circuit (means clearly lower than 1 Ohm) on the Vccint pins (on a new device we measure some 800 mV with a diode tester). Interestingly, it was still working in some way, some IO-Banks worked, others not, different after every configureation. The Gigabit-Transceiver was also still working. The first time we don't know when it ecactly happened, we just noticed that the chip got hot some time. The second time it happened during operation, it might correlate with the timepoint of plugging off the cable from the Gbit-Transceiver input.


We checked everything on the board, the voltages, the Power-On/Off supply sequencing and we think we can exclude an ESD-Problem. Our first intetion was over-voltage at the Vccint circuit. We use the APD2118 voltage controller, which are recommented by Xilinx and we tested the supply circuits extensively; we nearly can exclude an over-voltage.


Some basics for our board: We built a laser display. Therefore we use a GTP-Transceiver to receive an HD-SDI video signal (1.485 Gbit/s), which is distributed along the board via the FPGA to the 108 RGB-pixels, i.e. 324 lasers. Every laser is controlled by an individual I/O of the FPGA (via a laser driver), means we indeed are using most of the 500 available I/Os, but most of them are switched on and off max. just once per 256 clock cycles. The I/O drive strength is set to 4 mA, therefore we don't think that there accumulate harmful high currents. The system clock is 100 MHz. In normal operation, the FPGA consumes 1 to 2 W, so we don't need any forced cooling. The board temperature goes up to 40°C at ambient tempreature. So it seems everything is in the "green" range, we think we didn't exceed any specifications.


Did anybody notice a similar behavior? In the moment we can not find any cause for the damages, we even don't know where we shall search for. Or is this a known issue of the Artix-7? Helpful would be, if anybody experienced a similar damage and could tell us the reason, if found.

 

Thanks for any hint
Gerhard

 

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Scholar
Scholar
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Registered: ‎02-27-2008

l,

 

I suspect ESD.  This device I think is fip chip (smaller ones are wire bond).  So there are ESD protection cells all over the die, not just at the edges, and not just the IO banls.  Power pins too have ESD protection.

 

Even in the small wire-bond die, similar construction is used, and ESD protection cells are throughout the die on all connections to the package.

 

ESD damage may happen 30 days or more before it manefests.  In assembly, it may be damaged, and it may take a month of operation until break-down.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2012

ladyinred  informed --we can measure a short-circuit (means clearly lower than 1 Ohm) on the Vccint pins... FPGA is heating abnormally

 

As per about inputs (dead short & abnormal heating) It seems to that is dead short and FPGA damaged.Please check the below

 

1) Whether any voltage spikes are intermittently transferring to FPGA supply rail(At the time of measuring it might be OK. But spike for the fraction of second is enough to damage. So check complete system power supply quality)

2) Whether any two outputs short

3) Double check ESD precaution followed 100% or not

4) I am bit surprise if VCCINT is dead short to ground how some portion of FPGA is working. Please check any short is there below FPGA in betwee VCCINT and ground. Take  X-ray

 

 

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Visitor
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Registered: ‎10-07-2015

Thank you for the hints.

 

To 1) So far we can not find any reason for voltage spikes, but it is the most plausible reason.

 

to 2) is it possible that two shortened outputs can damage the FPGA core? Our Assumption was that in this case we would reconize a problem on the I/O supply rail, not on the Vccint Rail.

 

to 3) 100%

 

to 4) we measured the "nearly-schort" circuit at the dismounted device, to proof that the FPGA itself is damaged, but as you mentioned-surprisingly-some portion is still working. As far our knowledge about microelectronics we can imagine that just some ESD strukture is damaged, which are normally placed on the border of the chip, so that the core itself still might be operating. Also a hint for over voltage. Can you agree with this assuption?

 

Seems we should focus on the power supply quality...

 

 

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Scholar
Scholar
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Registered: ‎02-27-2008

l,

 

I suspect ESD.  This device I think is fip chip (smaller ones are wire bond).  So there are ESD protection cells all over the die, not just at the edges, and not just the IO banls.  Power pins too have ESD protection.

 

Even in the small wire-bond die, similar construction is used, and ESD protection cells are throughout the die on all connections to the package.

 

ESD damage may happen 30 days or more before it manefests.  In assembly, it may be damaged, and it may take a month of operation until break-down.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2012

Regarding hint 2):-  Yes your assumption is primarily correct. When 2 outputs short first that bank VCCO fails after some time (Not always depends upon heating time) VCCINT related part also may faildue to over heat

 

Please check ESD issues & Power supply portions thoroughly.

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Visitor
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Registered: ‎10-07-2015

Thank you for your hints, especially that one that ESD damage may happen long time before it manefests! We double-checked the entire chain beginning from the assembly with respect to ESD and we noticed that the two affected boards have been assembled on a different placement machine. Both of these boards failed in the first hours of operatin, whereas other boards, including one with a replacement-FPGA, run for hundreds of hours without any problem. Finally we got a hint which we can follow.

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Scholar
Scholar
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Registered: ‎02-27-2008

l,

 

Recently we had a customer complain that a power brick had blown out their equipment.  This reminded me of a case where the power wiring was faulty in the lab, and the ground was not 0 volts with respect to water pipes, metal fixtures, benches, etc.

 

That fault ended up being a mistake by the electrician, and in addition to being an electrocution hazard, was also blowing everything up.

 

Have an electrician double-check all power wiring for faults, or if there is any offset in the safety earth ground.

 

As for our power brick, we are still attempting to discover what the issue was.  At this point, it may also have been a faulty AC distribution to the outlest.  Or, it may be a faulty brick.

 

In any event, faulty AC power wiring can kill you, so this is a serious matter.  TuV, VDE, UL, etc. rating implies the design is correct, but anything may fail, and individual outlets may be wired incorrectly.

 

I started in electronics when tubes (valves) were still the dominant device.  I learned to keep one hand in my pocket at all times to prevent completing a circuit across my body (hand to hand circuit has your heart and lungs in the path).

 

ESD by comparison is just uncomfortable.  Either will make short work of integrated circuits.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
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Registered: ‎10-07-2015

Thank you for sharing your experience.

 

After some discussions, we have further questions. We can confirm that it is possible to generate an ESD damage, which manifests not before some time of operation. But isn't it very unlikely that it happened already two times (in our case 50%)?

 

Your post brings us to a further idea for the damages and we are interested in your opinion:

 

We are using a PC to generate the SDI signal. In the final product, we will use a cable equalizer to transform the electrical level on the cable to the proper (differential) levels for the GPT-input. In the lab we don't use any cable equalizer, just an attenuator and a DC-block, it works fine for the short distance and saves effort. It might be that the PC and the FPGA-board are on slightly different earth potentials. When plugging in the cable, there is a pike of compensating current, just short, but high, because there is no human body model, but a low-impedance connection via the cable. Is it possible that this pike ignites the ESD-structures? Can this ignition result in a chain-reaction and ignite also the ESD diodes up to the Vccint connections?

 

The contradiction is that the GPT transceiver and its supply pins are not affected. But the GPT is connected via an inductance with some ohmic resistance, which might limit the current and prevent damage. In contrast, the Vccint pins are connected directly to the more ore less powerful voltage regulators, additionally with high loads of capacities, a high current run over the ignited ESD diodes which results in overheating. Do you think this is possible or is it just a far-fetched theory? Anyway, we ensure that the PC and the board supply are connected to the same power outlet and we will insert some potential separating element to the SDI line, even in the lab.

 

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Scholar
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l,

 

Yes, to all.  The ESD structures will do nothing to prevent damage from midmatched grounds, supply volatges, or signal integrity issues (over shoot, under shoot, ringing).

 

Typically, a signal integrity analyisis is done using CAD tools (Mentor Hyperlynx, for example) to be sure you are not exceedinhg the absolute masimum pin voltages, or currents.

 

Protection of IO pins against external uncontrolled transients from plugging and unplugging cables, turning on and off equipment, requires transient absorbtion devices (diodesa, zener diodes, RC networks, gas tubes, etc. depending on the magnitude and duration of the transient).


The IO pin has intrinsic (built into the FET themselves) body diodes:  one from ground to the pin, and one to Vcco from the pin.  These will not protect the pin from transients beyond ~ 100 mA, and should not be relied upon for something like cable connect/disconnect transients as cables are able to store tremndous energies due to their capacitance (a long cable may be used as a destructive pulse generator, and is used in detsructive pulse generators).

 

Even LEDs and switches on the freont panel of equipment will conduct an ESD to the FPGA IO, so often designers use rC networks to isolate such destructive events (people have to touch switches) from reaching the IO pin.


Connector manufacturers use inductor, resistor, capacitor networks in connectors designed to filter EMI/RFI.  They also protect against ESD (think of EMI/RFI as what is created by ESD).

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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