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Visitor ruid61@gdms
Visitor
735 Views
Registered: ‎09-25-2018

Sys clock oscillator operational voltage not same as input port DDR3 bank

I have been asked to look into a clock issue on a Artix 7 design and jist of it is:

 

The 200 Mhz oscillator is running at 3.3V but the clock is feeding the DDR3 bank which is strapped to 1.35V. There is also the issue of the designer is using the SRCC input, not the MRCC inputs.

 

The 200 MHz differential output oscillator has a typical output common mode voltage of 1.3V and  a typical swing for each output of 0.6Vpp. This gives a typical output high of 1.6V with no information of the maximum which could occur. This clk is routed to an FPGA bank powered from 1.35V with an absolute maximum allowable input level of around 1.35 + 0.55 = 1.9V. 

 

I have captured the .XDC files where the sysclk property are massaged to get the right results but I am not sure if this is doable.

 

The top .xdc file has the following setup:

 

#set_property PACKAGE_PIN Y4 [get_ports SYS_CLK_clk_p]
#set_property PACKAGE_PIN AA4 [get_ports SYS_CLK_clk_n]

and then at the bottom

 

set_property IOSTANDARD LVDS_25 [get_ports SYS_CLK_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports SYS_CLK_clk_n]

 

the MIG specific xdc

 

# PadFunction: IO_L11P_T1_SRCC_34
set_property IOSTANDARD DIFF_SSTL135 [get_ports {sys_clk_p}]
set_property PACKAGE_PIN Y4 [get_ports {sys_clk_p}]

# PadFunction: IO_L11N_T1_SRCC_34
set_property IOSTANDARD DIFF_SSTL135 [get_ports {sys_clk_n}]
set_property PACKAGE_PIN AA4 [get_ports {sys_clk_n}]

 

I am hoping to get to the bottom of this a find a clean solution. The board is being designed so I have the opportunity to either moved the clock to the a different bank (if in the same column) or find away to clean it up before it enters the FPGA.

 

Please advise,

Rui

 

 

 

 

 

 

 

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4 Replies
691 Views
Registered: ‎01-22-2015

Re: Sys clock oscillator operational voltage not same as input port DDR3 bank

Hi Rui,

 

I’m not sure what questions you have.  Is something not working or is Vivado reporting errors?

 

Anyway, here is some information that might help.

 

First, you should give us the full part number for the Artix-7. Since your pins, (Y4 and AA4), are SRCC, I suspect you are using the 484-pin package. Comments in your XDC file suggest the pin-Y4 is also called IO_L11P_T1_SRCC_34 and the pin-AA4 is also called IO_L11N_T1_SRCC_34. You should download the “package file” for your Artix-7 from the Xilinx website <here> and verify that these pin names are correct. The pin names are important since they tell you: 1) the two pins are an LVDS pair (L11N/L11P), 2) the pins are clock-capable (SRCC), and 3) they are in bank 34.

 

I will assume that your SYS_CLK is coming into clock-capable pins on bank 34 (an HP bank) of the Artix-7.  Near table 1-43 in UG471 it says that the LVDS_25 I/O standard is available only in HR banks and that the LVDS I/O standard can be used in HP banks but VCCO must be 1.8V. If you were trying to do both LVDS-input and LVDS-output from HP bank 34 then you would have problems, since your VCCO=1.35V. However, you seem concerned only about LVDS-inputs. Near Table 1-44 in UG471 it says that LVDS inputs can be used “in I/O banks that are powered at voltage levels other than the nominal voltages” if certain criteria are met. The criteria are then listed, which include setting DIFF_TERM=FALSE for the inputs and making sure that the VIN Recommended Operating Conditions are met. This means that you cannot exceed the Absolute Maximum Ratings shown for VIN in Table 1 of DS181 and you must meet the V(IDIFF) and V(ICM) specifications shown in Table 11 of DS181.  

 

In summary, try the following XDC constraints in your top/main XDC file,

set_property PACKAGE_PIN Y4 [get_ports SYS_CLK_clk_p]
set_property PACKAGE_PIN AA4 [get_ports SYS_CLK_clk_n]
set_property IOSTANDARD LVDS [get_ports SYS_CLK_clk_p]
set_property DIFF_TERM FALSE [get_ports SYS_CLK_clk_p]

 

-and ensure that your SYS_CLK inputs to the Artix-7 meets specifications for VIN found in DS181.

 

The MIG constraints you have shown seem to contradict the above constraints - both in terms of the port name (eg. SYS_CLK_clk_p vs sys_clk_p) and in terms of the IOSTANDARD (eg. LVDS vs DIF_SSTL135).   You say the MIG constraints are from “MIG specific xdc”. So, I assume these constraints were automatically generated by the MIG/MIS setup wizard. I am not familiar with the MIG/MIS IP, but it seems that someone should rerun the setup wizard to resolve the constraint contradictions for FPGA pins Y4 and AA4.

 

Cheers,

Mark

Visitor ruid61@gdms
Visitor
660 Views
Registered: ‎09-25-2018

Re: Sys clock oscillator operational voltage not same as input port DDR3 bank

Hi Mark,

 

The current design "works" but I am concerned that we may be violating some limits and since we are in a respin cycle (post initial lab bring-up), I wanted to get this right and you seem to confirm my concerns that both the type of clock being used and the VCCO rails need to be addressed and the way the constrained were created and ultimately overridden.

 

You are correct that it is a 484 package; I have attached the actual pinout, meanwhile I will look further into the app notes you mentioned in your response.

 

Rui

 

DevicePort.JPG
OscPort.JPG
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Visitor ruid61@gdms
Visitor
586 Views
Registered: ‎09-25-2018

Re: Sys clock oscillator operational voltage not same as input port DDR3 bank

Hi Mark,

 

I apologize for the absence but other things came and wanted to find a solution for this that gave me a few options. I can start by mentioned that we can't change the interface to a 1.8V or 2.5V port so we have to stick with what we got. That being said, the options are:

 

1) Find a XO that would  operate at 1.8V hence giving a bit of margin within the max swing of the 1.35V VCCO

and

2) AC couple the clock and then DC bias it at VTT (0.675V); could do a thevinin bias, but I believe VTT (LDO) is a better solution.

 

Any thoughts?

 

Ru

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558 Views
Registered: ‎01-22-2015

Re: Sys clock oscillator operational voltage not same as input port DDR3 bank

Hi Ru,

 

I understand that your 200MHz oscillator has a differential digital (not analog) output – and that you need to attenuate and bias the oscillator output so that it is compatible with the LVDS inputs on an HP-bank of the Artix-7 that is powered with VCCO=1.35V.

 

This problem is similar to interfacing LVPECL to LVDS. That is, LVPECL outputs typically need to be attenuated and biased to make them compatible with LVDS. As explained nicely in the Texas Instruments (TI) document, SLLA101, this attenuate/bias can be accomplished with a circuit having architecture shown in the following figure (from SLLA101):

ECL_to_LVDS.jpg

 

Design equations in SLLA101 help you select resistor-values in the above circuit that not only attenuate/bias but maintain impedance matching (typ to 50 ohms). An input to the design equations is the Thevenin bias that you mentioned.

 

The SLLA101 circuit gives DC-coupling between a differential-digital transmitter and receiver. An AC-coupling circuit can also be used as described in TI document, SCAA059C SCAA059C. However, AC-coupling is only recommended for DC-balanced signals (like a 50% duty-cycle clock).

 

You could design your new board with the flexibility to use either AC-coupling or DC-coupling between the 200MHz oscillator and the LVDS inputs of the FPGA – depending on what resisters/capacitors/ref-voltages are installed.

 

Finally, if the output of the 200MHz oscillator is being sent to components on the board other than the FPGA then consider using a clock buffer (eg. Silicon Labs Si5330) to fanout/distribute the clock and further buffer/protect your expensive FPGA.

 

Cheers,

Mark

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