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Participant
Participant
2,632 Views
Registered: ‎06-15-2016

The lowest data speed the transceiver can support without error

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Hi everyone,

   I used transceiver IP to fulfil the STM1 in the 7 series FPGA. However, after I plug the fibre-optical several times, the transceiver IPcore cannot work in a right condition and it is very hard to recover it from that conditon(even I reset the ip core). The IP core cannot receive the right data.

   Here is the thing, the lowest line speed the transceiver can support is 500Mbps, and the line speed of the STM1 is 155.52Mbps, so I up-sampling the data to 622.08Mbps before the transceiver. Is that the reason for the problem? 

   Thank you. 

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Xilinx Employee
Xilinx Employee
4,685 Views
Registered: ‎02-14-2014

Hello @3008202060,

 

Instead of directly moving to implementation of STM1 transmission, is it possible to check the integrity of interface using either transceiver wizard IP or IBERT IP(PRBS data) in external loopback mode? You can check details about these IPs in below PG -

https://www.xilinx.com/support/documentation/ip_documentation/gtwizard/v3_6/pg168-gtwizard.pdf

https://www.xilinx.com/support/documentation/ip_documentation/ibert_7series_gtx/v3_0/pg132-ibert-7series-gtx.pdf

 

Regards,
Ashish
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Xilinx Employee
Xilinx Employee
4,686 Views
Registered: ‎02-14-2014

Hello @3008202060,

 

Instead of directly moving to implementation of STM1 transmission, is it possible to check the integrity of interface using either transceiver wizard IP or IBERT IP(PRBS data) in external loopback mode? You can check details about these IPs in below PG -

https://www.xilinx.com/support/documentation/ip_documentation/gtwizard/v3_6/pg168-gtwizard.pdf

https://www.xilinx.com/support/documentation/ip_documentation/ibert_7series_gtx/v3_0/pg132-ibert-7series-gtx.pdf

 

Regards,
Ashish
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Participant
Participant
2,594 Views
Registered: ‎06-15-2016

Hi Ashish,

   I am not very sure what do you mean by the integrity of interface. The interface of the hardware works well, because it can run the stm4 without error. 

   I once set the Ip core in loopback mode and the data was correct.

   I also use the oscilloscope to detect the signal at rx_p and rx_n on the hardware board and its signal is right. However, after the signal entering the transciever(the only function of the transciever is to convert the serial signal into parallel signal), the data is not right. 

   Can you draw any possible conclusion from the information I provided above?

   Thanks.

 

Regards,

Heng

QQ图片20170309142313.png
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Participant
Participant
2,589 Views
Registered: ‎06-15-2016

Problem solved. I added RXLPEN(used for rx-equalization mode selection) to the transceiver IP core, the problem I described above was solved. 

 

After I plugged the fibre optical for at least one hundred time, the data stream was right. 

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