10-15-2018 12:23 AM
How to prototype, through-silicon vias(TSV) module in FPGA. Just consider FPGA wire/link or any other way to module TSV in Artix 7 FPGA.
10-15-2018 01:48 PM
So, I am a little curious and concerned as to what the need for this information is. Would you care to share what you are trying to do here? I mainly ask because you question is in reference to Artix-7 and I am unaware of any documentation or Xilinx publication suggesting the use of TSVs for Artix-7 devices... As far as I know Virtex-7 were the ones with the silicon interposer and TSVs.
10-28-2018 02:28 AM
Design and implementation 3 Dimensional Network on chip architecture in FPGA. It uses vertical link(wire) as a TSV.