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Contributor
Contributor
380 Views
Registered: ‎02-25-2018

Through-silicon vias prototype in Artix 7 FPGA

How to prototype, through-silicon vias(TSV) module in FPGA. Just consider FPGA wire/link or any other way to module TSV in Artix 7 FPGA.

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Moderator
Moderator
346 Views
Registered: ‎09-18-2014

Re: Through-silicon vias prototype in Artix 7 FPGA

Khyam,

 

So, I am a little curious and concerned as to what the need for this information is. Would you care to share what you are trying to do here? I mainly ask because you question is in reference to Artix-7 and I am unaware of any documentation or Xilinx publication suggesting the use of TSVs for Artix-7 devices... As far as I know Virtex-7 were the ones with the silicon interposer and TSVs. 

 

Regards.

Tezz

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Contributor
Contributor
281 Views
Registered: ‎02-25-2018

Re: Through-silicon vias prototype in Artix 7 FPGA

Design and implementation 3 Dimensional Network on chip architecture in FPGA. It uses vertical link(wire) as a TSV.

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