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Explorer
Explorer
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Registered: ‎09-14-2018

Top-level design file becomes Non-module File

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Hello,

My top-level design file (Verilog) has been suddenly moved to Non-module Files. What could cause it? I have Vivado 2018.3.

Thank you.

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Explorer
Explorer
167 Views
Registered: ‎09-14-2018

Just found out that it was caused by the missed syntax typo in the signal list. So, the file was removed from the design hierarchy. It appears this may happen to any source file.

   

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Highlighted
Explorer
Explorer
168 Views
Registered: ‎09-14-2018

Just found out that it was caused by the missed syntax typo in the signal list. So, the file was removed from the design hierarchy. It appears this may happen to any source file.

   

View solution in original post

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