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arrubyyan
Observer
Observer
10,274 Views
Registered: ‎05-23-2014

Using external clock without PLL?

Hello,

 

I have an external clock which is 40Mhz. I want 20Mhz output out of that. initially I used PLL (or MMCM) to generate a 20Mhz clock out of that. However I found it power consuming. I was wondering is there a way that I can generate 20MHz "Without" using any PLLs and using IBUF & BUF manually? here aer some of my uncertanities:

1 - does it make any difference in terms of synchronization/delay to all the network if I use or not use the PLL?

2 - is it true that with this method I will use less power?

 

Thanks,

Aryan

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rjsefton
Explorer
Explorer
10,269 Views
Registered: ‎11-25-2014

In verilog:

 

reg clk20;

 

always @ (posedge clk40)

  clk20 <= ~clk20;

 

If you're using the 20MHz clock internally then feed it through a global buffer. If just going off chip then the global buffer is not needed.

 

1. With this method the phase between the 40MHz and 20MHz clocks will be unknown. If this matters then use the PLL.

 

2. This method will definitely save power vs. the PLL.

avrumw
Guide
Guide
10,248 Views
Registered: ‎01-23-2009

Another mechanism of generating a 20MHz internal clock that is in phase with the 40MHz clock is to use the BUFGCE. The resulting 20MHz clock will not be 50/50 duty cycle (in this case it will be 25%), but if the clock is being used only internally and you aren't using the falling edge (including an ODDR or IDDR), then this clock is perfectly fine for the FPGA.

 

You can see how this is done in this forum post.

 

Avrum

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arrubyyan
Observer
Observer
9,307 Views
Registered: ‎05-23-2014

Thank you.

 

It worked. 

Now how can I assign a correct timing constraint for that?

is it considered as a primary clock? (using create_clock command) or generated clock or virtual clock?

 

 

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avrumw
Guide
Guide
9,249 Views
Registered: ‎01-23-2009

You need to tell us which solution you implemented.

 

Clocks generated by an internal divider, either directly or using a BUFGCE/BUFHCE are derived clocks, and should be manually constrained with the create_generated_clock.

 

For the one generated by a flip-flop

 

create_generated_clock -source [get_pins clk_20_reg/C] -divide_by 2 [get_pins clk_20_reg/Q]

 

For the one generated by the BUFGCE/BUFHCE

 

create_generated_clock -source [get_pins BUFGCE_inst/I] -divide_by 2 [get_pins BUFGCE_inst/O]

 

(or whatever the name of the BUFGCE/BUFHCE instance is)

 

For all of these, you will first need to constrain the 40MHz clock coming in using a create_clock command.

 

Avrum

 

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arrubyyan
Observer
Observer
8,895 Views
Registered: ‎05-23-2014

Thank you, It worked. 

 

Aryan

P.S. I don't know why I can't accept it as a solution!

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