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Anonymous
Not applicable
7,440 Views

V7 programming problem

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Hi everybody,

 

we have the following  issue with programming a xc7v2000tflg1925-2 device. After the bit-file is successfully downloaded into the FPGA from iMPACT v14.2, the DONE pin of the device will change its output from 50mV to 100mV and the output ports (LVCMOS18) we are using will remain in high impedance state. Location constraints are in place and bank voltage of 1.8V is present. How should we interpret this behaviour, any hints are highly appreciated.

 

Best Regards,

Dimo

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Xilinx Employee
Xilinx Employee
9,612 Views
Registered: ‎01-03-2008

> DONE pin of the device will change its output from 50mV to 100mV

 

it sounds like you forgot to add a pullup on the DONE pin and without this going high the startup sequence won't finish and the IOs will remain tri-stated

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

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Scholar
Scholar
7,439 Views
Registered: ‎02-27-2008

File a webcase!

 

For goodness sakes.  You have a part that has ~ 7 billion transistors on it, and costs a lot of $$$$.  You will get real service and support if you just ASK for it?

 

OK?

 

We have over 400 Distributor and Xilinx FAE's out there.  This what they do (support paying customers).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
Not applicable
7,431 Views

Thanks, I did it. I tend to like to know the strengths of the different support channels.

You shouldn't underestimate the forums, you do some great job here.

It's not as deterministic as a WebCase, but sometimes it could be faster :)

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Scholar
Scholar
7,424 Views
Registered: ‎02-27-2008

Thanks for the compliment,

 

But the webcase channel is serious business:  lots of people are PAID to take care of issues.

 

I have always acted as the Xilinx customer advocate if the webcases are not doing what they should:  I am happy to escalate issues and get them looked at when appropriate.

 

Email directly at:  austin@xilinx.com with the webcase number.  I will review it, and take the appropriate actions.

 

As long as we stay on top of it, I get fewer than two or three such actions a year.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
9,613 Views
Registered: ‎01-03-2008

> DONE pin of the device will change its output from 50mV to 100mV

 

it sounds like you forgot to add a pullup on the DONE pin and without this going high the startup sequence won't finish and the IOs will remain tri-stated

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

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Scholar
Scholar
7,417 Views
Registered: ‎02-27-2008

Ed,

 

If it is that simple:  then that is wonderful.  I hope it is as simple as ading a 430 ohm pullup resistor!

 

(or, I belive you can select DRIVE_DONE as an option in bitgen)

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
Not applicable
7,412 Views

According to the schematic there is a 330 ohm pull-up resistor, which is ok as stated in the Configuration User Guide:

 

"External 330 ohm resistor circuits work in the 7 series FPGAs as they have on previous generations."

 

I will check tomorrow if there is really one on the board, you never know :)

Furthermore the pin is connected to an Astoria West Bridge's GPIO for status tracking.

We are doing this since generations of prototypes, so I do not expect any problems there, but

I will check if everything is ok with the chip configuration, not that the port changed to an output for some strange reasons.

 

Unfortunately I cannot make use of the DRIVE_DONE option with this FPGA:

 

"The DriveDONE option is not supported for stacked silicon interconnect technology devices."

 

But I will have a look at the DONE and INIT bits in the STATUS register and I will keep you updated. Thanks for the help.

 

Regards,

Dimo

 

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Anonymous
Not applicable
7,391 Views

Guys, problem solved. It was the Astoria Bridge :) Misconfiguration through dip-switches. Thanks a lot for narrowing it down. I closed the WebCase.

 

Regards,

Dimo

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Scholar
Scholar
7,379 Views
Registered: ‎02-27-2008

d,

 

We had concluded yesterday that your DONE pin was being pulled low (our best guess).


Glad to see our guess was correct!

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
Not applicable
7,374 Views

Absolutely

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