UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor manoj3050
Visitor
10,114 Views
Registered: ‎01-22-2016

VC709 SFP ports (GTH ip wizard cusomization)

Jump to solution

I'm currently having VC709 board and I'm trying to configure 7Series tranceiver ip to communicate through SFPports. It has 4 SFP ports and I need to loopback one port to another. I have optical cables, which comes with it and I have done the iBert test and it was sucessful. But however when I try to generate ip and generate the example desing and then put it to the board, it does not work. I cannot get any receiving data. I think I'm blind here and if anyone having a example design it would be great help. I configured correct GTH transceivers for the SFP ports and there is no issue. What I'm not understaing is how to give GTHref clock and drp clock. If you can help, please help me to sort this out.

Thanks.

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
19,382 Views
Registered: ‎02-16-2014

Re: VC709 SFP ports (GTH ip wizard cusomization)

Jump to solution

Hi @manoj3050

 

Your understanding is correct, The issue could be due to the reference clock.

For Quad 113 GTH transceivers if you selected the REFCLK source from the same quad, the possible options are through si5324 jitter attenuator or User SMA clock.

Capture.JPG

External user-provided GTH reference clock can be provided through these SMA connectors on board.

If you don't have external clock source available, you can open the IBERT reference design provided and see how the clock has been generated and connected to these SMA clock pins.

 

Hope this helps.

View solution in original post

3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
19,383 Views
Registered: ‎02-16-2014

Re: VC709 SFP ports (GTH ip wizard cusomization)

Jump to solution

Hi @manoj3050

 

Your understanding is correct, The issue could be due to the reference clock.

For Quad 113 GTH transceivers if you selected the REFCLK source from the same quad, the possible options are through si5324 jitter attenuator or User SMA clock.

Capture.JPG

External user-provided GTH reference clock can be provided through these SMA connectors on board.

If you don't have external clock source available, you can open the IBERT reference design provided and see how the clock has been generated and connected to these SMA clock pins.

 

Hope this helps.

View solution in original post

Visitor manoj3050
Visitor
9,978 Views
Registered: ‎01-22-2016

Re: VC709 SFP ports (GTH ip wizard cusomization)

Jump to solution

HI @pulim

Thank you for the information. I managed to get it working by using userclock which is clocked default at 156.25MHz and then connecting those to UserSMAClocks. Then exernally connected those with MGTRefClocks using SMA cables. Now it is working. But the problem is the receiving data is not anyware near close to transmitting data. Trackdata_out does not go high and but in the simulation, it goes high but still anyhow data does not match with the receiving data. Could you help with this too. (I'm running example design)

0 Kudos
5,594 Views
Registered: ‎08-26-2016

Re: VC709 SFP ports (GTH ip wizard cusomization)

Jump to solution

hi Manoj i am also trying same thing but i am trying t o use si5324 clock but i didnt use drp is this necessary  to use 

and if yours is working then plaz can you share your xdc file so that i also come to knw if you will share then i will be great help for me may be i am not putting correct xdc file i will attach my xdc or you can review my xdc  and tell me that is right or same thing wrong inside that 

thanks  

0 Kudos